STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 23
STEVAL-ISB005V1
Manufacturer Part Number
STEVAL-ISB005V1
Description
BOARD EVAL CHARGER ST7260/L6924D
Manufacturer
STMicroelectronics
Type
Battery Managementr
Specifications of STEVAL-ISB005V1
Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
L6924, ST72F63BK6M1
Primary Attributes
1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
Secondary Attributes
Powered by Wall Adaptor Also, LED Status Indicators
Input Voltage
5 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6924D, ST7260
Other names
497-8428
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STEVAL-ISB005V1
Manufacturer:
STMicroelectronics
Quantity:
1
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ST7260xx
Table 8.
BIt Name
3
2
1
0
N
C
Z
I
Interrupt mask
Negative
Zero (Arithmetic Management bit)
Carry/borrow
CC register description
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is
cleared. By default an interrupt routine is not interruptible because the I bit is set by
hardware at the start of the routine and reset by the IRET instruction at the end of the
routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1.
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.
Function
Central processing unit (CPU)
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