MT8VDDT3264HY-335G3 Micron Technology Inc, MT8VDDT3264HY-335G3 Datasheet - Page 14

• Manufacturer Part Number: MT8VDDT3264HY-335G3
• Description: MODULE DDR SDRAM 256MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT3264HY-335G3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13: I
DDR SDRAM component values only
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C
pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4;
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
andDQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
control inputs change only during Active READ or WRITE
commands
RC =
CK MIN; CKE = HIGH; Address and other control inputs changing
t
RC (MIN);
t
RC =
t
t
CK =
CK =
t
RC (MIN);
t
DD
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing
Specifications and Conditions – 256MB
t
t
IN
RC =
CK (MIN); DQ, DM and DQS inputs changing
t
= V
RC =
t
CK =
t
CK =
t
t
REF
CK =
RC (MIN);
OUT
t
RAS (MAX);
t
0.2V
for DQ, DQS, and DM
t
CK (MIN); CKE = (LOW)
CK (MIN); I
= 0mA
t
CK (MIN); CKE = LOW
t
CK =
t
OUT
CK =
t
CK (MIN); Address and
t
t
REFC =
REFC = 7.8125µs
= 0mA; Address and
t
CK (MIN); DQ, DM
t
RFC (MIN)
t
14
CK =
T
A
128MB, 256MB, 512MB (x64, SR)
+70°C; V
I
I
I
I
I
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD4W
SYM
I
I
DD3N
I
DD5A
I
I
DD2P
DD3P
DD4R
DD2F
DD0
DD1
DD5
DD6
DD7
DD
= V
1,000
1,360
1,400
1,400
2,040
3,280
DD
-335
400
240
480
32
48
32
200-PIN DDR SODIMM
Q = +2.5V ±0.2V
1,000
1,280
1,200
1,200
1,880
2,800
MAX
-262
360
200
400
32
48
32
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,160
1,200
1,200
1,880
2,800
-265
960
360
200
400
32
48
32
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 41
24, 43
24, 43
20, 42
43
44
43
20
9