MT48H16M32LFCM-75:A TR Micron Technology Inc, MT48H16M32LFCM-75:A TR Datasheet - Page 31

• Manufacturer Part Number: MT48H16M32LFCM-75:A TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H16M32LFCM-75:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1330-2

Figure 19:
Figure 20:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
WRITE Burst
WRITE-to-WRITE
Notes:
Notes:
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 21 on page 32, or each subsequent WRITE may be
performed to a different bank.
COMMAND
1. BL = 2. DQM is LOW.
COMMAND
1. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 22 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated). The PRECHARGE command should be issued
the last desired input data element is registered. The auto precharge mode requires a
t
In addition, when truncating a WRITE burst at high clock frequencies (
DQM signal must be used to mask input data for the clock edge prior to, and the clock
edge coincident with, the PRECHARGE command. An example is shown in Figure 23 on
page 33. Data n + 1 is either the last of a burst of two or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent command to the same bank
cannot be issued until
WR of at least one clock plus time, regardless of frequency.
ADDRESS
ADDRESS
CLK
CLK
DQ
DQ
WRITE
WRITE
BANK,
COL n
BANK,
COL n
D
T0
T0
D
n
n
IN
IN
n + 1
NOP
n + 1
NOP
T1
T1
D
D
IN
IN
t
RP is met.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
DON’T CARE
WRITE
BANK,
COL b
NOP
T2
T2
D
b
IN
31
DON’T CARE
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR after the clock edge at which
©2005 Micron Technology, Inc. All rights reserved.
t
CK < 15ns), the
Operations