MT48H16M32LFCM-75:A TR Micron Technology Inc, MT48H16M32LFCM-75:A TR Datasheet - Page 19

• Manufacturer Part Number: MT48H16M32LFCM-75:A TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H16M32LFCM-75:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1330-2

Commands
Table 5:
COMMAND INHIBIT
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table – Commands and DQM Operation
Notes 4 and 5 apply to all commands
Notes:
10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
12. BA0–BA1 select either the standard mode register or the extended mode register (BA0 = 0,
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear on pages 41–44;
these tables provide current state/next state information.
1. COMMAND INHIBIT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–A12 provide row address.
3. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto
4. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
5. All states and sequences not shown are reserved and/or illegal.
6. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
7. Applies only to read and write bursts with auto precharge disabled; this command is unde-
8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW.
9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
could coincide with data on the bus. However, the DQs column reads a don’t care state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
fined and should not be used for READ bursts with auto precharge enabled.
charged and BA0–BA1 are “Don’t Care.”
for CKE.
BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register;
other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to
the selected mode register.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
CS#
H
X
X
19
L
L
L
L
L
L
L
L
RAS# CAS# WE#
H
H
H
H
X
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
X
X
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
Bank/Row
©2005 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
X
X
High-Z
Active
Commands
Valid
DQs
X
X
X
X
X
X
X
X
Notes
6, 7, 8
10, 11
12
1
1
2
3
3
9