MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 41

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
(auto precharge
(auto precharge
Current State
Row active
disabled)
disabled)
Write
Read
Any
Idle
Truth Table – Current State Bank n, Command to Bank n
Notes: 1–6; notes appear below table
Notes: 1. This table applies when CKE
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
RAS# CAS# WE# Command (Action)
Idle:
Row active:
Read:
Write:
Precharging:
Row activating:
Read w/auto-
precharge enabled:
Write w/auto-
precharge enabled:
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
after
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should
be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Table 7, and according to Table 8 on
page 43.
t
XSR has been met (if the previous state was self refresh).
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LMR
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of an ACTIVE command and ends when
is met. Once
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
RP is met. Once
41
n-1
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
256Mb: x16, x32 Mobile SDRAM
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH (see Table 6 on page 40) and
t
RP has been met.
t
RCD has been met. No data
©2006 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Truth Tables
Notes
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RCD