MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 30

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITEs
Figure 18:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other com-
mands have been initiated, the DQs will remain High-Z and any additional input data
will be ignored (see Figure 19). A continuous page burst will proceed until terminated (at
the end of the page, it will wrap to the start address and continue).
A9, A11, A12
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe-
lined architecture. A WRITE command can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write accesses within a page can be per-
formed to the same bank, as shown in Figure 19 on page 31, or each subsequent WRITE
may be performed to a different bank.
BA[1:0]
A[8:0]
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
COLUMN
ADDRESS
BANK
30
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
©2006 Micron Technology, Inc. All rights reserved.
Operations