C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 96

• Manufacturer Part Number: C8051F987-GMR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F987-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F99x-C8051F98x
7.6.
Comparator0 C8051F99x-C8051F98x devices has an analog input multiplexer to connect Port I/O pins
and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for
Comparator0.
The comparator input multiplexers directly support capacitive touch switches. When the Capacitive Touch
Sense Compare input is selected on the positive or negative multiplexer, any Port I/O pin connected to the
other multiplexer can be directly connected to a capacitive touch switch with no additional external
components. The Capacitive Touch Sense Compare provides the appropriate reference level for detecting
when the capacitive touch switches have charged or discharged through the on-chip Rsense resistor. The
Comparator outputs can be routed to Timer2 or Timer3 for capturing sense capacitor’s charge and
discharge time. See Section “25. Timers” on page 276 for details.
Any of the following may be selected as comparator inputs: Port I/O pins, Capacitive Touch Sense
Compare, VDD Supply Voltage, Regulated Digital Supply Voltage (Output of VREG0) or ground. The
Comparator’s supply voltage divided by 2 is also available as an input; the resistors used to divide the
voltage only draw current when this setting is selected. The Comparator input multiplexers are configured
using the CPT0MX register described in SFR Definition 7.3.
Important Note About Comparator Input Configuration: Port pins selected as comparator inputs should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 213 for more Port I/O configuration details.
96
VDD
VDD
Comparator0 Analog Multiplexer
R
R
R
R
Digital Supply
CP0OUT
(1/3 or 2/3) x VDD
R
Voltage
P1.1
Capacitive
Compare
Sense
GND
Touch
½ x VDD
Figure 7.3. CP0 Multiplexer Block Diagram
CP0-
Input
MUX
CP0OUT
Rsense
Only enabled when
Capacitive Touch
Sense Compare is
selected on CP0+
Input MUX.
VDD
VDD
Rev. 1.1
R
R
R
R
CP0OUT
(1/3 or 2/3) x VDD
R
P1.0
VDD
Capacitive
Compare
GND
Touch
Sense
½ x VDD
CPT0MX
CP0+
Input
MUX
CP0OUT
Rsense
Only enabled when
Capacitive Touch
Sense Compare is
selected on CP0-
Input MUX.
+
-
VDD
GND