STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 66

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

Register description: New Map
6.18.3
6.18.4
6.18.5
6.19
6.19.1
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LRCK double trigger protection
Table 50.
This bit actively prevents double triggering of LRCLK.
Power-down
Table 51.
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power stage, then the master clock to all internal hardware except the I
block is gated. This places the IC in a very low power consumption state.The register state
is preserved once the device recovers from power-down.
External amplifier power-down
Table 52.
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the EAPD/FFX4B output pin when OCFG = 11.
Volume control registers (addr 0x17 - 0x1B)
Mute/line output configuration register (addr 0x17)
Bit
Bit
Bit
4
7
7
LOC1
D7
0
R/W
R/W
R/W
R/W
R/W
R/W
LRCK double trigger protection
IC power-down
External amplifier power-down
LOC0
D6
0
RST
RST
RST
1
1
0
Reserved
D5
0
Doc ID 018937 Rev 6
PWDN
EAPD
Name
Name
Name
LDTE
Reserved
D4
0
LRCLK double trigger protection enable
0: IC power-down low-power condition
1: IC normal operation
0: External power stage power-down active
1: Normal operation
C3M
D3
0
C2M
Description
Description
Description
D2
0
C1M
D1
0
STA381BWS
MMUTE
D0
0
2
C