STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 62

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

Register description: New Map
Note:
6.14.3
6.14.4
6.15
6.15.1
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To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into the STA381BWS data path before the desynchronization event
happens. At the same time any processing related to the I
only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
Delay serial clock enable
Table 35.
Channel input mapping
Table 36.
Each channel received via I
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
Configuration register C (addr 0x13)
FFX compensating pulse size register
Table 37.
Bit
Bit
Bit
Reserved
5
6
7
2
3
4
5
D7
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Delay serial clock enable
Channel input mapping
FFX compensating pulse size bits
Reserved
D6
0
RST
RST
RST
0
0
1
1
1
1
0
CSZ3
2
D5
0
S can be mapped to any internal processing channel via the
2
Doc ID 018937 Rev 6
DSCKE
S input channel to its corresponding processing channel.
Name
Name
Name
CSZ0
CSZ1
CSZ2
CSZ3
C1IM
C2IM
CSZ2
D4
1
0: Processing channel 1 receives left I
1: Processing channel 1 receives right I
0: Processing channel 2 receives left I
1: Processing channel 2 receives right I
When OM[1,0] = 11, this register determines the
size of the FFX compensating pulse from 0 clock
ticks to 15 clock periods.
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
CSZ1
D3
0
2
C configuration should be issued
CSZ0
Description
Description
Description
D2
2
1
S master devices
Reserved
2
D1
1
C operation due
STA381BWS
2
2
S input
S input
2
2
S input
S input
Reserved
D0
1