STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 153

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STA381BWSTR

Manufacturer Part Number
STA381BWSTR
Description
Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
Manufacturer
STMicroelectronics
Datasheet

Specifications of STA381BWSTR

Product Category
Audio DSPs
Rohs
yes
Operating Supply Voltage
4.5 V to 25.5 V
Operating Temperature Range
0 C to + 150 C
Mounting Style
SMD/SMT
Package / Case
VQFN-48
Snr
100 dB

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0
STA381BWS
7.22.5
7.22.6
Figure 43. Alternate function for INTLINE pin
Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
As per
million clock cycles puts the power bridge in tristate mode, independently from the fade-out
time. Using these registers it is possible to program this counter according to the following
table.
Table 171. PNDLSL bits configuration
Short-circuit check enable bit (address 0x4C, bit D0)
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section
PNDLSL[2]
“is the d evice in p ow erd o w n ?”
0
0
0
0
1
1
1
1
Section
7.22.2, the assertion of PWDN activates a counter that, by default, after 13
PNDLSL[1]
0
0
1
1
0
0
1
1
LPD
‘0 ’
Doc ID 018937 Rev 6
PNDLSL[2]
Y
N
0
1
0
1
0
1
0
1
Register description: Sound Terminal compatibility
7.20
Po w er B rid ge Fau lt
for more details.
LP D P
Default time (13M PLL clock cycles)
Default time divided by 128
0
1
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 2
Default time divided by 4
Default time divided by 8
LPD E
Fade-out time
0
1
IN T L IN E
153/171

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