STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 39

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
I
The STA381BWS supports the I
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA381BWS is always a slave device in all of its communications. It supports up to
400 kb/sec rate (fast-mode bit rate). The STA381BWS I
interface works properly only in the case that the master clock generated by the PLL has a
frequency 10 times higher compared to the frequency of the applied SCL signal.
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high-to-low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
Stop condition
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
the STA381BWS and the bus master.
Data input
During the data input the STA381BWS samples the SDA signal on the rising edge of clock
SCL. For correct device operation, the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA381BWS, the master must initiate
with a start condition. Following this, the master sends to the SDA line 8 bits (MSB first)
corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I
bus definition. In the STA381BWS the I
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode
and to 0 for write mode. After a START condition the STA381BWS identifies on the bus the
device address and if a match is found, it acknowledges the identification on SDA bus during
2
C bus specification
Doc ID 018937 Rev 6
2
C protocol via the input ports SCL and SDA_IN (master to
2
C interface has two device addresses depending on
2
C is a slave-only interface. The I
I
2
C bus specification
39/171
2
2
C
C