C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 260

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C8051F962-A-GM

Manufacturer Part Number
C8051F962-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F962-A-GM

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
DQFN-76
Mounting Style
SMD/SMT
Number Of Programmable I/os
57
Number Of Timers
4
C8051F96x
SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable
SFR Page = 0xF; SFR Address = 0xF5
260
Name
Reset
7:4
Bit
Type
3
2
1
0
Bit
PCLKACT3 Clock Enable Controls for Peripherals in Low Power Active Mode.
PCLKACT2 Clock Enable Controls for Peripherals in Low Power Active Mode.
PCLKACT1 Clock Enable Controls for Peripherals in Low Power Active Mode.
PCLKACT0 Clock Enable Controls for Peripherals in Low Power Active Mode.
Unused
Name
R/W
7
0
Read = 0b; Write = don’t care.
0: Clocks to the SmaRTClock, Pulse Counter, and PMU0 revert to the PCLKEN set-
ting in Low Power Active Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Active
Mode.
0: Clocks to Timer 0, Timer 1, Timer 2, and CRC0 revert to the PCLKEN setting in Low
Power Active Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Active Mode.
0: Clocks to ADC0 and PCA0 revert to the PCLKEN setting in Low Power Active
Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Active Mode.
0: Clocks to UART0, Timer 3, SPI0, and the SMBus revert to the PCLKEN setting in
Low Power Active Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Active
Mode.
R/W
6
0
R/W
5
0
R/W
Rev. 0.5
4
0
Function
3
0
PCLKACT[3:0]
2
0
R/W
1
0
0
0

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