C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 12

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
12
Figure 8.1. CIP-51 Block Diagram ......................................................................... 115
Figure 9.1. C8051F96x Memory Map .................................................................... 124
Figure 9.2. Flash Program Memory Map ............................................................... 125
Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126
Figure 10.1. Multiplexed Configuration Example ................................................... 134
Figure 10.2. Non-multiplexed Configuration Example ........................................... 135
Figure 10.3. EMIF Operating Modes ..................................................................... 135
Figure 10.4. Non-multiplexed 16-bit MOVX Timing ............................................... 139
Figure 10.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 140
Figure 10.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 141
Figure 10.7. Multiplexed 16-bit MOVX Timing ....................................................... 142
Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 143
Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 144
Figure 11.1. DMA0 Block Diagram ........................................................................ 147
Figure 12.1. CRC0 Block Diagram ........................................................................ 160
Figure 12.2. Bit Reverse Register ......................................................................... 167
Figure 13.1. Polynomial Representation ............................................................... 168
Figure 14.1. AES Peripheral Block Diagram ......................................................... 176
Figure 14.2. Key Inversion Data Flow ................................................................... 179
Figure 14.3. AES Block Cipher Data Flow ............................................................. 185
Figure 14.4. Cipher Block Chaining Mode ............................................................. 190
Figure 14.5. CBC Encryption Data Flow ................................................................ 191
Figure 14.6. CBC Decryption Data Flow ............................................................... 195
Figure 14.7. Counter Mode .................................................................................... 198
Figure 14.8. Counter Mode Data Flow .................................................................. 199
Figure 16.1. SFR Page Stack ................................................................................ 217
Figure 18.1. Flash Security Example ..................................................................... 247
Figure 19.1. C8051F96x Power Distribution .......................................................... 258
Figure 19.2. Clock Tree Distribution ...................................................................... 259
Figure 20.1. Step Down DC-DC Buck Converter Block Diagram .......................... 269
Figure 22.1. Reset Sources ................................................................................... 278
Figure 22.2. Power-On Reset Timing Diagram ..................................................... 279
Figure 23.1. Clocking Sources Block Diagram ...................................................... 286
Figure 23.2. 25 MHz External Crystal Example ..................................................... 288
Figure 24.1. SmaRTClock Block Diagram ............................................................. 295
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 303
Figure 25.1. Pulse Counter Block Diagram ........................................................... 312
Figure 25.2. Mode Examples ................................................................................. 313
Figure 25.3. Reed Switch Configurations .............................................................. 314
Figure 25.4. Debounce Timing .............................................................................. 318
Figure 25.5. Flutter Example ................................................................................. 320
Figure 26.1. LCD Segment Driver Block Diagram ................................................. 334
Figure 26.2. LCD Data Register to LCD Pin Mapping ........................................... 336
Figure 26.3. Contrast Control Mode 1 ................................................................... 338
Figure 26.4. Contrast Control Mode 2 ................................................................... 339
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