C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 219

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C8051F962-A-GM

Manufacturer Part Number
C8051F962-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F962-A-GM

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
DQFN-76
Mounting Style
SMD/SMT
Number Of Programmable I/os
57
Number Of Timers
4
SFR Definition 16.2. SFRPAGE: SFR Page
SFR Page = All Pages; SFR Address = 0xA7
Bit
7:0
Name
Reset
Type
Bit
SFRPAGE[7:0]
Name
7
0
SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 core will
automatically switch to the SFR Page that contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and
push/pop events of this stack are caused by interrupts (and not by reading/writ-
ing to the SFRPAGE register)
6
0
5
0
Rev. 0.5
SFRPAGE[7:0]
4
0
R/W
Function
3
0
2
0
C8051F96x
1
0
0
0
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