MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 91

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Fine adjustments can be made to the timer by varying the TRR up or down.
3.5.3 Timer 3 - Software Watchdog Timer
A watchdog timer is used to protect against system failures by providing a means to escape
from unexpected input conditions, external events, or programming errors. Timer 3 may be
used for this purpose. Once started, the watchdog timer must be cleared by software on a
regular basis so that it never reaches its timeout value. Upon reaching the timeout value, the
assumption may be made that a system failure has occurred, and steps can be taken to re-
cover or reset the system.
3.5.3.1 Software Watchdog Timer Operation
The watchdog timer counts from zero to a maximum of 32767 (16.67 seconds at 16.00 MHz)
with a resolution or step size of 8192 clock periods (0.5 ms at 16.00 MHz). This timer uses
a 16-bit counter with an 8-bit prescaler value.
The watchdog timer uses the main clock divided by 16 as the input to the prescaler. The
prescaler circuitry divides the clock input by a fixed value of 256. The output of this prescaler
circuitry is connected to the input of the 16-bit counter. Since the least significant bit of the
WCN is not used in the comparison with the WRR reference value, the effective value of the
prescaler is 512.
The timer counts until the reference value is reached and then starts a new time count im-
mediately. Upon reaching the reference value, the counter asserts the WDOG output for a
period of 16 master clock (CLKO) cycles, and issues an interrupt to the interrupt controller.
The value of the timer can be read any time.
To use the software watchdog function directly with the M68000 core, the timer 3 open-drain
output pin (WDOG) can be connected externally to the IPL2–IPL0 pins to generate a level
7 interrupt (normal mode), to IRQ7 (dedicated mode), or to the RESET and HALT pin. After
a total system reset, the WDOG pin function is enabled on pin PB7. The timer 3 counter is
automatically enabled after reset.
The software watchdog timer has an 8-bit prescaler that is not accessible to the user, a read-
only 16-bit counter, and a reference register (WRR).
3.5.3.2 Software Watchdog Reference Register (WRR)
WRR is a 16-bit register containing the reference value for the timeout. The EN bit of the
register enables the timer. WRR appears as a memory-mapped read-write register to the
user.
When operating in the MC68008 mode (BUSW is low), writing to the high byte of WRR will
disable the timer compare logic until the low byte is written.
Reset initializes the register to $FFFF, enabling the watchdog timer and setting it to the max-
imum timeout period. This causes a timeout to occur if there is an error in the boot program.
MOTOROLA
counter after reference is reached, ICLK = 01 to use the master clock, and RST = 1 to
enabled the timer).
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-41