MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 444

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

SCC Programming Reference
E.2.1.2.3 SCC Data Synchronization Register (DSR). This 16-bit register is located at off-
set $886 (SCC1) $896 (SCC2) and $8A6 (SCC3). Bits 14-12 of the DSR are used to pro-
gram the length of the last stop bit transmitted. These bits are decoded as follows:
DSR(14-12)—Fractional Stop Bits
E.2.1.2.4 UART Event Register (SCCE). This 8-bit register is located at offset $888
(SCC1) $898 (SCC2) and $8A8 (SCC3) on D15-D8 of a 16-bit data bus. The SCCE is used
to report events recognized by the UART channel. Bits must be cleared by the user to avoid
missing interrupt events. Bits are cleared by writing ones to the corresponding bit positions.
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
IDL—IDLE Sequence Status Changed
BRK—Break Character Received
CCR—Control Character Received
BSY—Busy Condition
E-22
111
110
101
100
011
010
001
000
0 = No interrupt.
1 = A change in the status of CTS was detected.
0 = No interrupt.
1 = A change in the status of CD was detected.
0 = No interrupt.
1 = A change in the status of the receive data serial line was detected.
0 = No interrupt.
1 = Break character received.
0 = No interrupt
1 = Control character received (with reject (R) character = 1) and stored in the receive
0 = No interrupt.
1 = A character was received and discarded due to lack of buffers.
control character register (RCCR).
16/16 (default value after reset).
15/16.
14/16.
13/16.
12/16.
11/16.
10/16.
9/16.
CTS
7
CD
6
MC68360 USER’S MANUAL
IDL
5
BRK
4
CCR
3
BSY
2
TX
1
RX
0
MOTOROLA