MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 369

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Reason 1: When doing character-by-character handling of a software echo operation, the
use of at least three BDs (i.e., really a three-byte software FIFO) takes care of the latency
between recognizing a character has come in and getting that character transmitted out as
other characters continue to come in. Use of four BDs in total gives plenty of software FIFO
margin.
Reason 2: Using two Tx BDs means that in a full-load situation, the next BD will always have
its ready bit set when the RlSC controller checks it, meaning that there will never be any add-
ed delay in getting characters transmitted out of the UART.
Reason 3: Using two Rx BDs gives extra time for the software to handle the interrupt for one
character while the next character is being received into the next buffer, and gives this ex-
ample the opportunity to show how to step through the BDs in software.
D.4.3 Assumptions about the System
The code, which was run on the ADS302 board, assumes that the MC68302 peripherals are
placed at the default position of $700000 (i.e., BAR is written with $700). It also assumes
that SCC3 is used. Either of the above assumptions can be modified if desired. The code
was assembled with a simple freeware M68000 assembler called X68000.
D.4.4 UART Features Not Discussed
The following UART capabilities were not discussed in this example: fractional stop bit trans-
mission, inserting flow control characters into the transmit data stream, recognizing special
control characters, using CTS and CD to control transmission and reception, use of an ex-
ternal clock, use of multiple bytes per buffer, sending breaks, sending idles before messag-
es, recognizing addresses, freezing transmission, idle timeout, and others. Refer to 4.5.11
UART Controller for more details.
D.4.5 UART Code Listing
MOTOROLA
* SI MP LE U A RT “E C H O” C OD E
* Register initialization values before execution:
*
* PC = 00030300 SR = 2700
* USP = 00080000 *ISP = 00004000 (Stack pointers not used)
*
* D1 = SCCE3 holding register
* D3 = count of characters received
* D4 = count of characters transmitted
* D5 = count of BSY conditions occurring (no receive buffers available)
* D6 = 1 or greater, if character(s) waiting to be transmitted, 0 otherwise
* A0 = current Rx BD pointer
* A1 = current “next TX byte” to send pointer
* A2 = current Tx BD pointer
* A3 = temp
* SCC3 Tx Buffer Descriptors initialization:
* 00700640 5000 0000 0003 0000
* 00700648 7000 0000 0003 0001 (wrap bit set)
* SCC3 Rx Buffer Descriptors initialization:
* 00700600 d000 0000 0003 0002
MC68302 USER’S MANUAL
MC68302 Applications
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