MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 158

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
The buffer descriptors may have their ready/empty bits set at any time. Notice that the com-
mand register (CR) does not need to be accessed following power-on reset. An SCC should
be disabled and re-enabled (see 4.5.10 Disabling the SCCs) after any dynamic change in
its parallel I/O ports or serial channels physical interface configuration. A full reset using the
RST bit in the CR is a comprehensive reset that may also be used.
4.5.8 Interrupt Mechanism
Interrupt handling for each of the SCC channels is configured on a global per-channel basis
in the interrupt pending register (IPR), the interrupt mask register (IMR), and the interrupt in-
service register (ISR). Within each of these registers, one bit is used to either mask or report
the presence of a pending or in-service interrupt in an SCC channel. However, an SCC in-
terrupt may be caused by a number of events. To allow interrupt handling for SCC-specific
events, further registers are provided within the SCCs.
Up to eight events can cause the SCC to interrupt the processor. The events differ in accor-
dance with the SCC protocol chosen. The events are handled independently for each chan-
nel by the SCC event register (SCCE) and the SCC mask register (SCCM). All unmasked
event bits must be cleared in order for the corresponding IPR bit to be cleared. The interrupt
handler typically reads the event register, and then immediately clears those bits that it will
deal with during the interrupt handler.
4.5.8.1 SCC Event Register (SCCE)
This 8-bit register is used to report events recognized by any of the SCCs. On recognition
of an event, the SCC will set its corresponding bit in the SCC event register (regardless of
the corresponding mask bit in the SCC mask register). The SCC event register is a memory-
mapped register that may be read at any time. A bit is cleared by writing a one (writing a
zero does not affect a bit's value).
4-38
3. Write SCON (see 4.5.2 SCC Configuration Register (SCON)).
4. Write SCM (SCC Mode) but do not set the ENT or ENR bits yet (see 4.5.3 SCC Mode
5. Write DSR as required if a protocol other than HDLC is used (see specific protocol sec-
6. Initialize the required values in the general-purpose parameter RAM (see 4.5.6 SCC
7. Initialize the required values in the protocol-specific parameter RAM (see specific pro-
8. Clear out any current events in SCCE, if desired (see specific protocol section).
9. Write SCCM to enable the interrupts in SCCE that should reach the interrupt controller
10. Write IMR in the interrupt controller to enable the SCC interrupt to the interrupt con-
11. Set the ENR and/or ENT bits in SCM (see 4.4.3 PCM Highway Mode).
(i.e., NMSI, PCM, GCI, IDL modes). If IDL or GCI is chosen in SIMODE, write SIMASK
in the serial channels physical interface (see 4.4.5 Serial Interface Registers).
Register (SCM)).
tion).
Parameter RAM Memory Map).
tocol section).
(see specific protocol section).
troller (see 3.2.5.3 Interrupt Mask Register (IMR)).
MC68302 USER’S MANUAL
MOTOROLA