PNX1301 PHILIPS [NXP Semiconductors], PNX1301 Datasheet - Page 344

• Manufacturer Part Number: PNX1301
• Description: Media Processors
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Floating-point compare greater or equal
SYNTAX
FUNCTION
DESCRIPTION
the second argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-
point values; the result is an integer. If an argument is denormalized, zero is substituted for the argument before
computing the comparison, and the IFZ flag in the PCSW is set. If
corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a
side-effect of any floating-point operation but can only be reset by an explicit
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates
ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
[ IF rguard ] fgeq rsrc1 rsrc2
if rguard then {
}
if (float)rsrc1 >= (float)rsrc2 then
else
fgeq
fgeqflags
rdest
rdest
fgeq
Initial Values
operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
1
0
operation computes the exception flags that would result from an individual
fgeq r30 r40
fgeq r30 r30
IF r10 fgeq r60 r30
IF r20 fgeq r60 r30
fgeq r30 r60
fgeq r30 r61
fgeq r50 r55
fgeq r60 r65
fgeq r50 r50
rdest
Operation
r80
r90
r120
r121
r125
r126
r127
PRELIMINARY SPECIFICATION
r100
r110
PNX1300/01/02/11 DSPCPU Operations
fgeq
r80
r90
no change, since guard is false
r110
r120
r121
r125
r126
r127
writepcsw
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
1
1
causes an IEEE exception, the
0
1
0, INV flag set
1
1, IFZ flag set
1
igeq fgeqflags fgtr
readpcsw writepcsw
ATTRIBUTES
operation. The update of
SEE ALSO
Result
fgeq
.
fgeq
fcomp
146
No
—
2
1
3
A-46