PNX1301 PHILIPS [NXP Semiconductors], PNX1301 Datasheet - Page 114

• Manufacturer Part Number: PNX1301
• Description: Media Processors
• Manufacturer: PHILIPS [NXP Semiconductors]

PNX1300/01/02/11 Data Book
90 MHz. The PLL is enabled and programmed as de-
scribed in
DDS clock rate is set by the VO_CLOCK. FREQUENCY
field according to the equation shown in
VO_CLK frequency can be a divider or multiplier of f
as determined by the PLL subsystem settings.
Low-jitter clock mode is automatically entered whenever
FREQUENCY[31] = 1. If FREQUENCY[31] = 0, the DDS
operates at 1/3 the rate (for compatibility with TM-1000
code), and FREQUENCY must be set as shown in
Figure
The DDS synthesizer maximum jitter can be computed
as follows:
Example of jitter values can be found in
Table 7-2. Jitter values for common DSPCPU MHz
7-4
Figure 7-6. DDS low-jitter oscillator frequency.
Figure 7-7. DDS slow speed oscillator frequency
Figure 7-8. Interlaced timing—NTSC analog sync. signals.
f
Video
Lines
Vertical
Sync
DSPCPU
(MHz)
jitter
143
166
FREQUENCY
7-7.
Section
FREQUENCY
=
---------------------------- -
9 f
1
(nSec)
0.777
0.669
jitter
7.19.
D SPCPU
Blanking
1
PRELIMINARY SPECIFICATION
=
2
31
19 20
=
+
f
DSPCPU
(MHz)
1/2 Line Interlace Offset
---------------------------- -
9 f
---------------------------- -
3 f
180
200
f
f
D DS
Field 1
DD S
DSPCPU
D SPCPU
One Line
Active Video
2
2
Table
Figure
32
32
(nSec)
0.617
0.555
jitter
7-2.
7-6. The
DDS
,
One Frame
262 263
7.8
The EVO emits a serial byte-data stream used by
CCIR 656 devices to generate a displayed image.
Figure 7-9
laced image. The field and line numbers are shown for
reference.
Interlaced images are generated by the display hardware
by controlling the vertical retrace timing. For reference,
Figure 7-8
interlaced frame timing illustrating the analog vertical re-
trace signal. The vertical retrace signal for the second
field begins in the middle of the horizontal line that ends
the first field. This causes the first line of the second field
to begin halfway across the display screen and the lines
of the second field to be scanned between the lines of the
first field, resulting in an interlaced display.
The analog timing required to generate the interlaced
signal is supplied by the display device. The CCIR 656
digital video signals generated by the EVO use frame
synchronization timing and do not generate any vertical
retrace timing.
7.8.1
The EVO generates pixels according to CCIR 656 timing
in YUV 4:2:2 co-sited format and outputs these pixels as
shown in
two, with four bytes per two pixels. Each pair of pixels
has two luminance bytes (Y0, Y1) and one pair of chromi-
nance bytes (U0, V0) arranged in the sequence shown.
The chrominance samples U0 and V0 are sampled spa-
tially co-sited with luminance sample Y0. For PAL or
NTSC video, pixels are generated at a nominal rate of
13. 5 Mpix/sec. (27 MB/sec.). Pixels are clocked out on
the positive edge of VO_CLK.
7.8.2
The CCIR 656 line timing is shown in
line begins with an EAV code, a blanking interval and an
SAV code, followed by the line of active video. The EAV
code indicates end of active video for the previous line,
and the SAV code indicates start of active video for the
current line.
Blanking
IMAGE TIMING
Figure
CCIR 656 Pixel Timing
CCIR 656 Line Timing
shows a timing diagram of NTSC-compatible
shows an NTSC-compatible, 525-line inter-
7-10. Pixels are generated in groups of
Field 2
282
Active Video
Philips Semiconductors
Figure
525 1
7-11. Each