ch7019 Chrontel, ch7019 Datasheet - Page 65

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LODP (bit 7) of register LODA activates the LVDS Outputs Driver Pull-Down during power-down.
LVDS PLL Spread Spectrum Control
LODST (bit 7) of register LPSSC controls the LVDS Output Drive Source Termination.
LVDS Power Down & Loop Filter Resister
LODPDB[1:0] (bits 1-0) of register LPDLFR control the LVDS Output Power Down per the following table:
Note 1: Outputs are tri-stated in power down mode unless LODP (address 74h, bit 7) is ‘1’, in which case outputs are
LPPRB (bit 2) of register LPDLFR controls the LVDS PLL Reset.
201-0000-048
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
LODPE
LODP
LODST = 0 => 100Ω (typ.) shunt disabled between LVDS outputs LDCx and LDCx*, also LLxC and LLxC*
LPPRB
TYPE:
TYPE:
BIT:
BIT:
pulled to ground.
LODPDB1
= 1 => 100Ω (typ.) shunt enabled between LVDS outputs LDCx and LDCx*, also LLxC and LLxC*
Table 37: LVDS Output Power Down
LODST
FRSTB
= 0 =>
= 1 =>
= 0 =>
= 1 =>
= 0 =>
= 1 =>
R/W
R/W
0
0
1
1
Rev. 2.4,
0
1
7
7
Pull up reduced by 33% and pull down reduced by 66%.
Default value
Pull-down devices not active
Pull-down devices active
LVDS PLL is reset
Normal operation
LODPDB0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
LPLF2
12/18/2006
R/W
R/W
0
1
0
1
6
0
6
0
LDC[6:4] & LL2C , LL2C* path
Power Down
Power Down
Power On
Power On
LPLF1
R/W
R/W
5
0
5
1
1
1
LPLF0
R/W
R/W
4
0
4
0
LPPDN
R/W
R/W
3
0
3
1
LDC[2:0] , LL1C & LL1C* path
Power Down
Power On
Power Down
Power On
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
LPPRB LODPDB1 LODPDB0
R/W
R/W
2
0
2
1
1
1
R/W
LPSSC
75h
1
LPDLFR
76h
8
R/W
1
0
1
0
CH7019B
R/W
R/W
0
0
0
1
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