ch7019 Chrontel, ch7019 Datasheet - Page 41

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The
entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus SAV[8] contained in the Text Enhancement
register (03h, bit 5). This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels.
Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of Hsync to the first active data must
be a multiple of two clocks.
Horizontal Position Register
Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally
centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus HP[8] contained in the
Text Enhancement register (03h, bit 4). Increasing values move the displayed image position right, and decreasing values
move the image position left.
Vertical Position Register
Register VP is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered
image on screen. The entire bit field, VP[8:0], is comprised of this register VP[7:0] plus VP[8] contained in the Text
Enhancement register (03h, bit 3). The value represents the TV line number (relative to the VGA vertical sync) used to
initiate the generation and insertion of the TV vertical interval (i.e. the first sequence of equalizing pulses). Increasing
values delay the output of the TV vertical sync, causing the image position to move up on the TV screen. Decreasing
values, therefore, move the image position DOWN. Each increment moves the image position by one TV line
(approximately 2 input lines). The maximum value that should be programmed into VP[8:0] is the number of TV lines
per field minus one half (262 or 312). When panning the image up, the number should be increased until (TVLPF-1/2) is
reached, the next step should be to reset the register to zero. When panning the image down the screen, decrement the
VP[8:0] value until the value zero is reached. The next step should set the register to TVLPF-1/2, and then decrement
for further changes.
201-0000-048
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
R/W
R/W
HP7
VP7
Rev. 2.4,
7
0
7
0
R/W
R/W
12/18/2006
HP6
VP6
6
1
6
0
R/W
R/W
HP5
VP5
5
0
5
0
R/W
R/W
HP4
VP4
4
1
4
0
R/W
R/W
HP3
VP3
3
0
3
0
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
R/W
R/W
HP2
VP2
2
0
2
0
R/W
R/W
HP1
VP1
HP
05h
8
VP
06h
8
1
0
1
0
CH7019B
R/W
R/W
HP0
VP0
0
0
0
0
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