ch7019 Chrontel, ch7019 Datasheet - Page 50

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Input Clock Register
X1CMD[3:0] (bits 3-0) of register IC control the delay applied to the XCLK1 signal before latching input data D1[11:0]
per the following table. 1 unit is approximately 70 ps worst case.
BLKEN (bit 6) of register IC controls the Black Level control register update during the vertical sync blanking period. A
value of ‘0’ disables the Black Level control register update. A value of ‘1’ enables the Black Level control register
update.
GPIO Control Register
50
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Table 28: Delay applied to XCLK1 before latching input data D1
GOENB1 GOENB0 GPIOL1
Reserved
X1CMD3
R/W
R/W
7
0
7
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BLKEN
X1CMD2
R/W
R/W
6
1
6
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Reserved Reserved
X1CMD1
R/W
R/W
5
0
5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
GPIOL0
X1CMD0
R/W
R/W
4
0
4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1CMD3 X1CMD2 X1CMD1 X1CMD0
Reserved Reserved
Adjust phase of Clock relative to
Data
0 unit, XCLK1 ahead of Data
1 unit, XCLK1 ahead of Data
2 unit, XCLK1 ahead of Data
3 unit, XCLK1 ahead of Data
4 unit, XCLK1 ahead of Data
5 unit, XCLK1 ahead of Data
6 unit, XCLK1 ahead of Data
7 unit, XCLK1 ahead of Data
0 unit, XCLK1 behind Data
1 unit, XCLK1 behind Data
2 unit, XCLK1 behind Data
3 unit, XCLK1 behind Data
4 unit, XCLK1 behind Data
5 unit, XCLK1 behind Data
6 unit, XCLK1 behind Data
7 unit, XCLK1 behind Data
R/W
R/W
3
1
3
0
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
201-0000-048
R/W
R/W
2
0
2
0
POUTE
R/W
R/W
IC
1Dh
5
GPIO
1Eh
6
Rev. 2.4, 12/18/2006
1
0
1
0
CH7019B
POUTP
R/W
R/W
0
0
0
0