ch7019 Chrontel, ch7019 Datasheet - Page 44

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
TV PLL M Value Register
Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input to
the TV PLL phase detector when the CH7019 is operating in clock master mode. The entire bit field, M[8:0], is
comprised of this register M[7:0] plus M[8] contained in the TV PLL Control register (09h, bit2). In slave mode, an
external pixel clock is used instead of the 14.31818MHz frequency reference, but the division factor is also controlled by
M[8:0]. In slave mode, the value of ‘M’ is internally set to 1. A table of values (Table 25) versus display mode is given
following the PLLN register description.
TV PLL N Value Register
Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase detector,
when the CH7019 is operating in clock master mode. The entire bit field, N[9:0], is comprised of this register N[7:0]
plus N[9:8] contained in the TV PLL Control register (09h, bits 3 and 4). In slave mode, the value of ‘N’ is internally set
to 1. The pixel clock generated in clock master modes is calculated according to the equation Fpixel = Fref * [(N+2) /
(M+2)]. When using a 14.31818MHz frequency reference, the required M and N values for each mode are shown in
Table 25 below:
44
DEFAULT:
DEFAULT:
Mode
0
1
2
3
4
5
6
7
8
SYMBOL:
SYMBOL:
Table 25: TV PLL M and N values vs. Display Mode
TYPE:
TYPE:
BIT:
BIT:
VGA Resolution,
TV Standard,
Scaling Ratio
512x384, PAL, 5:4
512x384, PAL, 1:1
512x384, NTSC, 5:4
512x384, NTSC, 1:1
720x400, PAL, 5:4
720x400, PAL, 1:1
720x400, NTSC, 5:4
720x400, NTSC, 1:1
640x400, PAL, 5:4
R/W
R/W
M7
N7
0
0
7
7
R/W
R/W
M6
N6
6
0
6
1
N
10-bits
(dec)
20
9
126
110
53
86
106
70
108
R/W
R/W
M5
N5
5
1
5
1
N
10-bits
(hex)
0x14
0x09
0x7E
0x6E
0x35
0x56
0x6A
0x46
0x6C
R/W
R/W
9-bits
(dec)
M4
N4
89
63
63
33
M
13
26
33
61
4
1
4
1
4
M
9-bits
(hex)
0x0D
0x04
0x59
0x3F
0x1A
0x21
0x3F
0x21
0x3D
R/W
R/W
M3
N3
3
1
3
1
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
201-0000-048
R/W
R/W
M2
N2
2
1
2
1
R/W
R/W
PLLM
0Ah
8
PLLN
0Bh
8
Rev. 2.4, 12/18/2006
M1
N1
1
1
1
1
CH7019B
R/W
R/W
M0
N0
0
1
0
0