ch7019 Chrontel, ch7019 Datasheet
ch7019
Manufacturer Part Number
ch7019
Description
Ch7019 Tv Encoder / Lvds Transmitter
Manufacturer
Chrontel
Datasheet
1.CH7019.pdf
(79 pages)
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Chrontel
201-0000-048
Features
TV-Out:
• VGA to TV conversion supporting up to 1024x768
• Macrovision™ 7.1.L1 copy protection support
• Two variable-voltage digital input ports.
• Simultaneous LVDS and TV output.
• True scale rendering engine supports under-scan in all
• Enhanced text sharpness and adaptive flicker removal
• Support for NTSC and PAL TV formats
• Outputs CVBS, S-Video, RGB and YPrPb
• Support for SCART connector
• TV / Monitor connection detect
• Output video switch for easy wiring to connectors
LVDS-Out:
• Single / Dual LVDS transmitter
• Dual LVDS supports pixel rate up to 330Mpixels/sec.
• LVDS low jitter PLL accepts emission reduction input
• LVDS 18-bit output
• 2D dither engine
• Panel protection and power down sequencing
• Programmable power management
• Support for second CRT DAC bypass mode
• Four 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 128-pin LQFP package
TV output resolutions †¥
with up to 7 lines of filtering ¥
when both 12-bit input ports are ganged together
XCLK1,XCLK1*
XCLK2,XCLK2*
H1,V1, DE1
H2,V2, DE2
D2[11:0]
D1[11:0]
VREF1
FLD1
FLD2
Rev. 2.4,
CH7019 TV Encoder / LVDS Transmitter
12
3
12
2
2
3
Latch &
Latch &
Demux
Demux
Clock,
Clock,
Data,
Data,
Sync
Sync
12/18/2006
Figure 1: CH7019 Functional Block Diagram
Serial Port Control and Misc. Functions
Dither Engine
Deflicker / Text Enhancement /
Scaling / Scan Conversion /
TV Encode
TV Timing
LVDS PLL
TV PLL
LVDS Encode /
General Description
The CH7019 is a Display Controller device which accepts two
digital graphics input data streams. One data stream outputs
through an LVDS transmitter to an LCD panel, while the other
data stream is encoded for NTSC or PAL TV and outputs
through a 10-bit high speed DAC. The TV encoder device
encodes a graphics signal up to 1024x768 resolution and
outputs the video signals according to NTSC or PAL standards.
The LVDS transmitter operates at pixel speeds up to 165MHz
per link, supporting 1600x1200 panels at 60Hz refresh rate.
The device can also accept one graphics data stream over two
12-bit wide variable voltage ports which support nine different
data formats including RGB and YCrCb (RGB must be used
for LVDS output). A maximum of 330M pixels per second can
be output through dual LVDS links.
The TV-Out processor will perform non-interlaced to interlaced
conversion with scaling, flicker filtering, and encoding into any
of the NTSC or PAL video standards. The scaler and flicker
filter are adaptive and programmable for superior text display.
Eight graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal under-scan capability in all
modes.
integrated to create outstanding video quality.
provided for Macrovision
bypass modes are included which allow the TV DACs to be
used as a second CRT DAC.
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels.
commonly used formats, including those detailed in the
OpenLDI and the SPWG specifications.
outputs on three to six differential channels.
Serialize
A high accuracy low jitter phase locked loop is
DAC's
10-bit
Four
Transmit
LVDS
XTAL
TM
. In addition to TV encoder modes,
4
¥ Patent number 5,914,753
† Patent number 5,781,241
4
2
6
2
2
6
2
2
DACA[3:0]
CH7019B
P-OUT
BCO/VSYNC
C/HSYNC
DACB[3:0]
LDC[2:0],LDC*[2:0]
LL1C,LL1C*
ENAVDD, ENABKL
LDC[6:4],LDC*[6:4]
LL2C, LL2C*
XI/FIN,XO
Data is encoded into
Serialized data
Support is
1
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