ch7019 Chrontel, ch7019 Datasheet - Page 61

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Power Sequencing T4
Register PST4 defines the Power Off time (T4), the required time prior to power off after the valid LVDS Clock and
Data become tri-stated or disabled. The entire bit field, TPOFF[8:0], is comprised of these bits, TPOFF[7:0], plus
TPOFF8 contained in the Power Sequencing T3 register (address 69h. Refer to Figure 18 and Table 15 in section 2.4.4.
The range is 1ms to 512ms in increments of 1ms.
Power Sequencing T5
TPPWD[5:0] (bits 5-0) of register PST5 define the Power Cycle time (T5), the waiting time required prior to enabling
power on after power has been off. Refer to Figure 18 and Table 15 in section 2.4.4. The range is 0 to 1600ms in
increments of 50ms.
C4GP[5:4] (bits 7-6) of register PST5 define the GPIO C4 Control bits [5:4]. The entire bit field is made up of these bits
C4GP[5:4] plus C4GP[3:2] contained in the GPIO Driver Type register (6Ch, bits 7-6) and C4GP[1:0] contained in the
GPIO Data [5:2] register (6Dh, bits 7-6). Refer to the description of the GPIOD register (6Dh) for more information.
GPIO Driver Type
GPIODR[5:0] (bits 5:0) of register GPIODR defines the output driver type for pins GPIO[5:0] – CMOS or Open Drain.
A value of ‘0’ sets corresponding GPIO output to CMOS output type , and a value of ‘1’ sets corresponding GPIO output
to Open Drain type.
201-0000-048
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
TPOFF7 TPOFF6
C4GP5
C4GP3
R/W
R/W
R/W
Rev. 2.4,
0
1
1
7
7
7
C4GP4
C4GP2
12/18/2006
R/W
R/W
R/W
6
0
6
1
6
1
TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0
GPIODR5 GPIODR4 GPIODR3 GPIODR2 GPIODR1 GPIODR0
TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
4
0
4
1
4
0
R/W
R/W
R/W
3
0
3
0
3
1
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
R/W
R/W
R/W
0
2
2
0
2
1
R/W
R/W
R/W
PST4
6Ah
8
PST5
6Bh
8
GPIODR
6Ch
8
1
0
1
0
1
1
CH7019B
TPOFF0
R/W
R/W
R/W
0
0
0
1
0
1
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