ch7009b Chrontel, ch7009b Datasheet - Page 48

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ch7009b

Manufacturer Part Number
ch7009b
Description
Ch7009 Dvi / Tv Output Device
Manufacturer
Chrontel
Datasheet

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CHRONTEL
8. T
8.1 Clock - Master, Sync - Master Mode
48
Table 30. Timing and Voltage Levels for Clock - Master, Sync - Master Mode
t
t
t
t
t1
t2
t3
Symbol
S
H
R
F
P-OUT
H
V
XCLK
XCLK*
D[11:0]
DE
IMING
Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
Pout, H, V (when configured as outputs) Output Rise Time
Pout, H, V (when configured as outputs) Output Fall Time
XCLK & XCLK* rise/fall time w/15pF load
D[11:0] & DE rise/fall time w/15pF load
Hold time:
P-OUT to HSYNC, VSYNC delay
I
NFORMATION
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
OH
OL
OH
OL
IH
IL
IH
IL
IH
IL
IH
IL
Figure 18: Timing for Clock - Master, Sync - Master Mode
Parameter
t3
t
R
64 PIXELS
1 VGA
Line
t
F
t1
Min
201-0000-035 Rev 3.31, 11/4/2004
t
R
see Table 29
see Table 29
see Table 29
see Table 29
P0a
Typ
1.5
1
1
t
S
P0b
t
S
P1a
t
F
P1b
Max
CH7009B
t
H
P2a
P2b
t2
Unit
ns
ns
ns

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