ch7009b Chrontel, ch7009b Datasheet - Page 37

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
GPIO Control Register
Bit 0 of register GPIO controls the polarity of the P-OUT signal. A value of ‘0’ does not invert the clock at the output pad.
Bit 1 of register GPIO enables the P-OUT signal. A value of ‘1’ drives the P-OUT clock signal out of the
P-OUT / TLDET* pin. A value of ‘0’ disables the P-OUT signal.
Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-OUT pin. A value of ‘1’
allows the hot plug detect circuit to pull the P-OUT / TLDET* pin low when a change of state has taken place on the hot
plug detect pin. A value of ‘0’ disables the interrupt signal. The two control bits HPIE and POUTE should not be enabled
(set to ‘1’) at the same time.
Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7009 to release the
P-OUT / TLDET* pin. When a hot plug interrupt is asserted by the CH7009 (P-OUT / TLDET*) the CH7009 driver
should read register 20h to determine the state of the DVI termination. After having read this register, the HPIR bit should
be set high to reset the circuitry, and then set low again.
Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register values are
driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register values can be
read to determine the level forced into the corresponding GPIO pins.
Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to an
input, and a value of ‘0’ sets the corresponding pin to an output.
Input Data Format Register
Bits 2-0 of register IDF select the input data format. See Input Interface on page 10 for a listing of available formats.
Bit 3 of register IDF controls the horizontal sync polarity. A value of ‘0’ defines the horizontal sync to be active low, and
a value of ‘1’ defines the horizontal sync to be active high.
Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and a
value of ‘1’ defines the vertical sync to be active high.
Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7009, and a value of ‘1’
defines sync to be output from the CH7009. The CH7009 can only output sync signals when operating as a VGA to TV
encoder, not when operating as a DVI transmitter.
Bit 6 of register IDF signifies when the CH7009 is to decode embedded sync signals present in the input data stream
instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the H
and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
201-0000-035 Rev 3.31, 11/4/2004
DEFAULT
DEFAULT
SYMBOL
SYMBOL
TYPE
TYPE
BIT
BIT
GOENB1 GOENB0 GPIOL1 GPIOL0
R/W
R/W
IBS
7
1
7
0
R/W
DES
R/W
6
1
6
0
SYO
R/W
R/W
5
0
5
0
R/W
R/W
VSP
4
0
4
0
HPIR
R/W
R/W
HSP
3
0
3
0
HPIE
IDF2
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
POUTE
IDF1
R/W
R/W
CH7009B
1
0
1
0
GPIO
1Eh
8
IDF
1Fh
8
POUTP
IDF0
R/W
R/W
37
0
0
0
0