ch7009b Chrontel, ch7009b Datasheet - Page 10

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
5. I
Two distinct methods of transferring data to the CH7009 are described. They are:
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7009 is latched with both edges of the clock
(also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate, the data applied to the
CH7009 is latched with one edge of the clock. The polarity of the pixel clock can be reversed under serial port control.
5.1 Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the
input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK* waveform represents the
input clock for the multiplexed data, clock at 1X pixel rate method.
Regarding the CH7009 timing specifications, please see Figure 18 - Figure 20 for details.
10
XCLK
XCLK
XCLK
XCLK
D[11:0]
DE
H
V
•
•
NPUT
Multiplexed data, clock input at 1X pixel rate
Multiplexed data, clock input at 2X pixel rate
I
NTERFACE
Figure 5. Interface Timing
1 VGA Line
64 P-OUT
201-0000-035 Rev 3.31, 11/4/2004
CH7009B