ch7009b Chrontel, ch7009b Datasheet - Page 35

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Calculated Increment Value Register
Registers CIV contain the value that was calculated by the CH7009 as the sub-carrier increment value. The entire bit
field, CIV[25:0], is comprised of these three registers plus the MSB values contained in the CIV Control register, bits
CIV25 and CIV24. This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below. CIV
registers are Read Only.
Register Contents
10hCIV[25:24]
11hCIV[23:16]
12hCIV[15:8]
13hCIV[7:0]
Clock Mode Register
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency (dual
edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge clocking mode).
Bit 1 of register CM controls the P-OUT clock frequency. A value of ‘0’ generates a clock output at the pixel frequency,
while a value of ‘1’ generates a clock at twice the pixel frequency.
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7009. A value of ‘1’ inverts the XCLK signal
at the input of the device. This control is used to select which edge of the XCLK signal to use for latching input data.
Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* = ‘1’),
the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to determine the
TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to the TV PLL. The M
and N TV PLL divider values are forced to one.
201-0000-035 Rev 3.31, 11/4/2004
DEFAULT
DEFAULT
SYMBOL
SYMBOL
TYPE
TYPE
BIT
BIT
CIV#
X
R
7
7
CIV#
X
R
6
6
CIV#
X
R
5
5
CIV#
X
R
4
4
M/S*
CIV#
R/W
X
R
3
0
3
CIV#
MCP
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
X
R
2
2
0
CIV#
PCM
R/W
CH7009B
X
R
1
1
0
CIV
11h –
13h
8 each
CM
1Ch
4
XCM
CIV#
R/W
35
X
R
0
0
0