ch7009b Chrontel, ch7009b Datasheet - Page 41

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
DVI PLL Charge Pump Control Register
Bits 1-0 of register TPCP control the DVI PLL charge pump. The default value shown on Table 23 is recommended.
Bits 3-2 of register TPCP control the DVI PLL post scale divider. (see Table 23).
Bit 4 of register TPCP is a reserved bit and should be left at the default value.
Bits 7-5 of register TPCP control the DVI transmitter output drive level. The default value shown on Table 23 is
recommended.
DVI PLL Divider Register
Bits 3-0 of register TPD control the DVI PLL feedback divider. (see Table 23).
Bits 5-4 of register TPD control the DVI PLL feed forward divider. (see Table 23).
Bits 7-6 of register TPD are reserved bits and should be left at the default value.
DVI PLL Supply Control Register
Bits 5-0 of register TPVT control the DVI PLL supply voltage. (see Table 23).
Bits 7-6 of register TPVT are reserved bits, and should be left at the default value.
Please see Table 23 for the default values in terms of the frequency ranges.
201-0000-035 Rev 3.31, 11/4/2004
DEFAULT
DEFAULT
DEFAULT
SYMBOL
SYMBOL
SYMBOL
TYPE
TYPE
TYPE
BIT
BIT
BIT
Reserved Reserved TPFFD1 TPFFD0 TPFBD3 TPFBD2 TPFBD1
Reserved Reserved
DVID2
R/W
R/W
R/W
7
1
7
0
7
0
DVID1
R/W
R/W
R/W
6
1
6
0
6
0
DVID0
TPVT5
R/W
R/W
R/W
5
1
5
0
5
1
TPVT4
DVII TPPSD1 TPPSD0
R/W
R/W
R/W
4
0
4
1
4
1
TPVT3
R/W
R/W
R/W
3
0
3
0
3
0
TPVT2
R/W
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
1
2
1
2
0
TPVT1
TPCP1
R/W
R/W
R/W
CH7009B
1
0
1
1
1
0
TPCP
33h
7
TPD
34h
6
TPVT
35h
6
TPFBD0
TPVT0
TPCP0
R/W
R/W
R/W
41
0
0
0
0
0
0