ch7009b Chrontel, ch7009b Datasheet - Page 11

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
5.2 Input Clock and Data Formats
The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock latching data
on both clock edges, or a 2X clock latching data with a single edge. The data received by the CH7009 can be used to drive
the DVI output, the VGA to TV encoder, or directly drive the DAC’s. The multiplexed input data formats are (IDF[2:0]):
IDF
0
1
2
3
4
For multiplexed input data formats, either both transitions of the XCLK/XCLK* clock pair, or each rising or falling edge
of the clock pair (depending upon MCP bit, rising refers to a rising edge on the XCLK signal, a falling edge on the
XCLK* signal) will latch data from the graphics chip. The multiplexed input data formats are shown in the figures below.
The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream, which contains either RGB or YCrCb formatted
data. The input data rate is 2X the pixel rate, and each pair of Pn values (eg; P0a and P0b) will contain a complete pixel
encoded as shown in the tables below. It is assumed that the first clock cycle following the leading edge of the incoming
horizontal sync signal contains the first word (Pxa) of a pixel, if an active pixel was present immediately following the
horizontal sync. This does not mean that active data should immediately follow the horizontal sync, however. When the
input is a YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance data, with
the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and
the following Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent
upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats,
and 16 for Y and 128 for CrCb in YCrCb formats.
201-0000-035 Rev 3.31, 11/4/2004
Description
12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1)
12-bit multiplexed RGB2 input (24-bit color), (multiplex scheme 2)
8-bit multiplexed RGB input (16-bit color, 565)
8-bit multiplexed RGB input (15-bit color, 555)
8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed)
CH7009B
11