ch7009b Chrontel, ch7009b Datasheet - Page 22

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
5.4 Hot Plug Detection
The CH7009 has the capability of signaling to the graphics controller when the termination of the DVI outputs has
changed. The operation of this circuit is as follows. The HPDET input pin of the CH7009 should be connected to pin 16
of the DVI connector. When a DVI monitor is connected to the DVI connector, this pin will be pulled high (above 2.4
volts). When a DVI monitor is not connected to the DVI connector, the internal pull-down on the HPDET pin will pull
low. When the HPDET is low, the DVI output driver will be shut down. The CH7009 will detect any transition at the
HPDET pin. When the HPIE (Hot Plug Interrupt Enable) bit in serial port register 1Eh is high, the CH7009 will pull low
on the P-OUT / TLDET* pin. When the HPIE2 (Hot Plug Interrupt Enable 2) bit in serial port register 20h is high, the
CH7009 will pull low on the GPIO[1] / TLDET* pin. This should signal the driver to read the DVIT bit in register 20h to
determine the state of the HPDET pin. The P-OUT / TLDET pin will continue to pull low until the driver sets the HPIR
(Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low. In order to reset the HPIR
bit high, DVIP and DVIL bits of register 49h[7:6] must first be set to ’11’.
6. R
The CH7009 is controlled via a serial port. The serial port bus uses only the SPC clock to latch data into registers, and
does not use any internally generated clocks so that the device can be written to in all power down modes. The device
retains all register states.
The CH7009 contains a total of 37 registers for user control. A listing of non-Macrovision control bits is given below
with a brief description of each.
6.1 Non-Macrovision Control Registers Map
The non-Macrovision controls are listed below, divided into four sections: general controls, input / output controls, DVI
controls, and VGA to TV controls. A register map and register description follows.
• General Controls
ResetIB
ResetDB
PD[7:0]
VID[7:0]
DID[7:0]
TSTP[1:0]
• Input/Output Controls
XCM
XCMD[3:0]
MCP
PCM
POUTP
POUTE
HPIE, HPIE2
HPIR
IDF[2:0]
IBS
DES
SYO
VSP
HSP
TERM[5:0]
BCOEN
BCO[2:0]
BCOP
GPIOL[1:0]
GOENB[1:0]
SYNCO[1:0]
DACG[1:0]
DACBP
XOSC[2:0]
22
EGISTER
Software serial reset
Software datapath reset
Power down controls (DVIP, DVIL, , TVD, DACPD[3:0], Full, Partial)
Version ID register
Device ID register
Enable/select test pattern generation (color bar, ramp)
XCLK 1X, 2X select
Delay adjust between XCLK and D[11:0]
XCLK polarity control
P-OUT 1X, 2X select
P-OUT clock polarity
P-OUT enable
Hot plug detect interrupt enable
Hot plug detect interrupt reset
Input data format
Input buffer select
Decode embedded sync (TV-Out data only)
H/V sync direction control (for TV-Out modes only)
V sync polarity control (sync polarity to DVI is not changed)
H sync polarity control (sync polarity to DVI is not changed)
Termination detect/check (DVI, DACT3, DACT2, DACT1, DACT0, SENSE)
Enable BCO Output
Select output signal for BCO pin
BCO polarity
Read or write level for GPIO pins
Direction control for GPIO pins
Enables/selects sync output for Scart and bypass modes
DAC gain control
DAC bypass
Crystal oscillator adjustments
C
ONTROL
201-0000-035 Rev 3.31, 11/4/2004
CH7009B