s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 5

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

DC and Operating Characteristics . . . . . . . . . . . 121
AC Operating Conditions . . . . . . . . . . . . . . . . . 124
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Functional Description . . . . . . . . . . . . . . . . . . . . . 131
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135
December 23, 2004 S71PL129Jxx_00_A5
Common ............................................................................................................... 121
16M pSRAM ......................................................................................................... 122
32M pSRAM ........................................................................................................ 122
64M pSRAM ........................................................................................................ 123
128M pSRAM ....................................................................................................... 123
Test Conditions (Test Load and Test Input/Output Reference) ....... 124
Read Timings ...................................................................................................... 126
Write Timings .................................................................................................... 127
Power Down ....................................................................................................... 131
Power Down Program Sequence ................................................................. 132
Address Key ....................................................................................................... 132
Read Operation ..................................................................................................135
Write Operation ............................................................................................... 136
Figure 45. Output Load ..................................................... 124
Figure 46. Timing Waveform of Read Cycle(1)...................... 126
Figure 47. Timing Waveform of Read Cycle(2)...................... 126
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127
Figure 49. Write Cycle #1 (WE# Controlled) ........................ 127
Figure 50. Write Cycle #2 (CS1# Controlled) ....................... 128
Figure 51. Timing Waveform of Write Cycle(3) 
(CS2 Controlled) .............................................................. 128
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ...................................................................... 129
pSRAM Type 7
A d v a n c e
I n f o r m a t i o n
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
Power Down Parameters ............................................................................... 137
Other Timing Parameters ............................................................................... 137
AC Test Conditions .........................................................................................138
AC Measurement Output Load Circuits ...................................................138
Read Timings .......................................................................................................139
Write Timings ......................................................................................................141
Read/Write Timings ..........................................................................................144
Figure 53. AC Output Load Circuit – 16 Mb.......................... 138
Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb .......... 138
Figure 55. Read Timing #1 (Basic Timing) .......................... 139
Figure 56. Read Timing #2 (OE# Address Access................. 139
Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 140
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 141
Figure 60. Write Timing #1 (Basic Timing) .......................... 141
Figure 61. Write Timing #2 (WE# Control).......................... 142
Figure 62. Write Timing #3-1
(WE#/LB# /UB# Byte Write Control) .................................. 142
Figure 63. Write Timing #3-3
(WE#/LB# /UB# Byte Write Control) .................................. 143
Figure 64. Write Timing #3-4
(WE#/LB# /UB# Byte Write Control) .................................. 143
Figure 65. Read/Write Timing #1-1 (CE1# Control) ............. 144
Figure 66. Read / Write Timing #1-2 
(CE1# / WE# /OE# Control) ................................................ 144
Figure 67. Read / Write Timing # 2 (OE#, WE# Control) ....... 145
Figure 68. Read / Write Timing #3
(OE# , WE# , LB# , UB# Control) ........................................ 145
Figure 69. Power-up Timing #1 ......................................... 146
Figure 70. Power-up Timing #2 ......................................... 146
Figure 71. Power Down Entry and Exit Timing ..................... 146
Figure 72. Standby Entry Timing after Read or Write ............ 147
Figure 73. Power Down Program Timing (for 32M/64M Only). 147
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