s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 22

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

22
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#
pins are both held at V
range than V
± 0.3 V, the device is in standby mode, but the standby current is greater. The
device requires standard access time (t
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at V
the device reduces current to the stated sleep mode specification.
Characteristics”
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/ BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the
for the timing diagram.
When the OE# input is at V
(except for RY/BY#) are placed in the highest Impedance state
CC3
SS
IL
in
±0.3 V, the device draws CMOS standby current
but not within V
“DC Characteristics”
READY
IH
AC Characteristics
.) If CE1# or CE# 2 and RESET# are held at V
(during Embedded Algorithms). The system can thus monitor RY/
represents the automatic sleep mode current specification.
SS
IO
±0.3 V, the standby current is greater.
± 0.3 V. (Note that this is a more restricted voltage
IH
RH
A d v a n c e
represents the CMOS standby current specification.
, output from the device is disabled. The output pins
after the RESET# pin returns to V
S29PL129J for MCP
tables for RESET# parameters and to
READY
CE
) for read access when the device is in
I n f o r m a t i o n
(not during Embedded Algorithms).
(I
CC4
IH
). If RESET# is held
, but not within V
IH
.
I
CC5
Figure 13
IH
S29PL129J_MCP_00_A0 June 4, 2004
in
RP
before
ACC
, the
“DC
IO
+