msm7730 Oki Semiconductor, msm7730 Datasheet - Page 5

• Manufacturer Part Number: msm7730
• Description: Wireless Lan Baseband Controller
• Manufacturer: Oki Semiconductor

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The MSM7730 can be configured to operate with V30HL, V53A, and 80C186 processor types. The proces-
sor configuration is determined from the P_CONF field in the Device Configuration register. The following
table shows how each processor is selected. No external circuitry is required between the processor and
the MSM7730.
Selecting the Processor Mode
In each processor mode, the bus interface module:
The module also synchronizes data and control signals to the internal clocks, and interfaces the external
processor to the host interface and processor interrupt control modules.
The 80C186 and V53A processors contain their own clock generator modules and divide-by logic. In
these modes, the MSM7730 generates a clock (X1) at twice the normal operating frequency. The processor
divides this frequency by two (X1/2). Then this clock is used for synchronization of all interface signals.
In V30HL processor mode, the MSM7730 generates the clocks for the internal modules as well as the pro-
cessor. A 16-MHz clock is used during normal operation. This frequency is reduced when the MSM7730
enters either the Hibernate or Smart Hibernate modes. In Hibernate mode the clock frequency is reduced
from 16 MHz to 500 KHz. In Smart Hibernate mode the frequency is reduced to 125 KHz.
Shared RAM Interface
A shared memory interface is provided for the buffering of packets and the storage of processor code and
data. Memory sizes range from 32K words to 128K words in 32K-word increments.
Both 16-bit (word) and 8-bit memory accesses are supported. The MSM7730 and the host computer sup-
port only word accesses to memory. The processor supports both byte and word accesses to memory.
Selection of byte or word transfers occurs on a per-cycle basis and depends on the state of address bit 0
(PD[0]) and the PUBEN signal as shown in the table below.
Selecting the Data Transfer Size
• Interprets the external bus cycles
• Generates the appropriate signals based on the processor mode,
• Passes access requests to the host interface module, the shared RAM arbiter, and the baseband
registers.
PD[0]
0
0
1
1
P_CONF 2:0
000
001
010
011
100
PUBEN
0
1
0
1
Host-only mode. No local processor.
V30HL local processor mode.
80C186 local processor mode.
Reserved
V53A local processor mode.
Word transferred on PD[15:0]
Even byte transferred on PD[7:0]
Odd byte transferred on PD[15:8]
Invalid
Processor Mode
Oki Semiconductor
Transfer Type
MSM7730
3