msm7730 Oki Semiconductor, msm7730 Datasheet - Page 13

• Manufacturer Part Number: msm7730
• Description: Wireless Lan Baseband Controller
• Manufacturer: Oki Semiconductor

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PIN DESCRIPTIONS
Host Interface Signal Descriptions (PCI and ISA)
Processor Interface Signal Descriptions (V30HL, V53A, and 80C186)
HPACKN
HIOIS16N
HIOWRN
HIORDN
HIREQN
HOEN
HREGN
HA[8:0]
HCEN[2:1]
HD[15:0]
HRST
HWAITN
HWEN
HCE1N
HCE2N
PD[17:0]
PST[2:0]
PCLK/PCLKOUT
PINTN
PCSN
PREADYN
PRESETN
PUBEN
PREAD
Pin Name
Pin Name
Output
Output
Input
Input
Output
Input
Input
Input
Input
Bidirectional
Input
Output
Input
Input
Output
Bidirectional
Input
Input/Output
Output
Input
Output
Output
Input
Input
Direction
Direction
This signal is asserted when the card is selected and can respond to an I/O read cycle at the address on the
address bus.
This signal is asserted whenever the access on A[8:0] corresponds to an I/O location which is capable of a 16-
bit access.
Indicates an I/O write cycle.
Indicates an I/O read cycle.
Active low interrupt request and ready/busy indicator prior to I/O card pin replacement.
Output enable signal asserted during memory read operations. Assertion of this signal causes memory data to
be driven onto HD[15:0].
Assertion of this signal indicates an access to either attribute memory or I/O space.
Least significant 9 bits of the PC-card address bus. All other address bits are ignored.
Active low card enable signals. HCEN[1] selects even numbered bytes. HCEN[2] selects odd numbered bytes.
Bidirectional data bus. Even numbered bytes appear on HD[7:0]. Odd numbered bytes appear on HD[15:8].
Active high reset input.
Active low wait output. This signal is asserted if an access is requested that cannot complete immediately.
Active low memory write enable input. Indicates a write to either attribute memory or common memory as
determined by the state of the HREGN signal.
Assertion of this signal indicates that a DMA transfer is in progress.
Indicates the ISA shared interrupt status.
Bidirectional multiplexed address/data bus driven during the T1 clock state. PD[17:16] are inputs only.
Bus status code that indicates the current cycle type. These inputs must be held HIGH when reset is asserted.
Clock output of the MSM7730 to which all bus interface signals are synchronized. Frequency is 16 MHz during
normal operation but is reduced when in hibernate mode. These two pins must be connected together for
proper operation.
This signal is generated by the host and processor interrupt module.
Processor chip select.
Active high ready indication from the MSM7730.
This signal is controlled by the host and is asserted based on the state of the PRSTN bit in the H_CTL register.
Upper byte enable. Indicates that a byte of data is to be transferred on PD[15:8].
Indicates a read cycle when HIGH, and a write cycle when LOW.
Description
Description
Oki Semiconductor
MSM7730
11