msm7730 Oki Semiconductor, msm7730 Datasheet - Page 18

• Manufacturer Part Number: msm7730
• Description: Wireless Lan Baseband Controller
• Manufacturer: Oki Semiconductor

MSM7730 Register Map (Continued)
16
0x50
0x52
0x58
0x5A
0x60
0x64
0x66
0x68
0x6A
0x6C
0x6E
MSM7730
Offset
Byte
MAC Control
Oki Semiconductor
Register
Group
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
16
16
16
16
16
16
16
16
16
16
16
Width
(bits)
TSF Timer
TSF Timer
TSF Comparator 1
TSF Comparator 2
Add TSF Time
NAV Timer
Backoff Timer
Response Timer
Tick Timer
Timer Control
Slot Time
Register Name
This register works in conjunction with the register at address 0x52 to
construct a 32-bit microsecond timer used for time stamps in received frames
and beacon transmissions.
This register works in conjunction with the register at address 0x50 to
construct a 32-bit microsecond timer used for time stamps in received frames
and beacon transmissions.
This register contains the least-significant 16 bits of a 24-bit TSF timer value.
This register works in conjunction with the register at address 0x5A. The 16
bits of the TSF Comparator 1 register and the 8-bits of the TSF Comparator 2
register comprise the 24-bit TSF comparator value.
This register contains the most-significant 8 bits of a 24-bit TSF timer value.
This register works in conjunction with the register at address 0x58. The 16
bits of the TSF Comparator 1 register and the 8-bits of the TSF Comparator 2
register comprise the 24-bit TSF comparator value. This 8-bit value is
contained in the lower 8 bits of this register. The upper 8 bits are reserved.
Hardware uses the lower 10 bits of this register to determine the length of
time that the TSF timer is disabled. This value can be modified by software.
This 16-bit register contains a 1-µs resolution timer that maintains the virtual
carrier sense mechanism. The timer is automatically loaded by the MAC but
can be modified by software.
This register is loaded automatically by the MAC from transmit frame header
structures. If a backoff condition occurs, the counter begins decrementing
until it reaches zero.
Contains a timeout value, in increments of 32 µs, after which the MAC aborts
the transmit frame if it does not receive an acknowledgment.
Sets the interval time in milliseconds at which interrupts are generated.
Contains enable and status information for each of the timers in the MAC
control register group.
Contains the value used to determine the length of slots required for random
backoff.
Description