msm7730 Oki Semiconductor, msm7730 Datasheet - Page 16

• Manufacturer Part Number: msm7730
• Description: Wireless Lan Baseband Controller
• Manufacturer: Oki Semiconductor

MSM7730 REGISTER MAP
The following table lists the registers in the MSM7730.
MSM7730 Register Map
14
0x00
0x10
0x12
0x00
0x02
0x04
0x00
0x02
0x08
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
MSM7730
Offset
Byte
Configura-
tion
PCMCIA
ISA Host
Global Con-
trol
EEPROM
PHY/Radio
Oki Semiconductor
Register
Group
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Width
(bits)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
Device Configuration
Configuration Option
Configuration and Status
Host Control (H_CTL)
Host Address (H_ADDR)
Host Data (H_DATA)
Version Number
Global Control
Processor Interrupt Control
EEPROM Data
EEPROM Address Control
PHY Configuration
Synthesizer Program
Synthesizer Program
Radio Control (RAD_CTL)
Radio Delay (RAD_DLYS)
Radio Power (RAD_PWR)
Radio Power (RAD_PWR)
Register Name
Stores serial EEPROM size and sets host interface and processor interface
modes.
Stores interrupt, reset, and configuration index information.
Stores general cycle status information, including interrupts and power-
down.
Contains ISA reset, host interface and processor interface interrupt
information
Contains the address in shared memory to be accessed by the H_DATA
register.
Stores host data information.
Contains the MSM7730 version number (0xC3). This register is read-only.
Contains mapping information for baseband control registers and MAC/PHY
enables.
Contains host interrupt, processor interrupt, and interrupt enable information.
This register is a buffer that contains data being transferred to and from the
EEPROM.
Contains EEPROM enable and cycle type information.
Contains Modem and PHY revision information as well as transmit and
receive status. The 3-bit MSEL field defines the type of modem operation..
Contains the least-significant 16 bits of the 32 bits used for synthesizer
programming. This register is used in conjunction with the other SYN register
located at 0x14.
Contains the most-significant 16 bits of the 32 bit s used for synthesizer
programming. This register is used in conjunction with the other SYN register
located at 0x12.
Contains radio configuration and transmit and receive status information.
Contains programmable delay parameters between the TXC[1:0] and RXC1
signals.
Determines when the TXC2 signal is asserted if the power control word is
selected. Two control bits in the PHY control word of a transmit packet
determine which one of four 8-bit values is used. This register is used in
conjunction with the other PAD_PWR register located at 0x1C.
Determines when the TXC2 signal is asserted if the power control word is
selected. Two control bits in the PHY control word of a transmit packet
determine which one of four 8-bit values is used. This register is used in
conjunction with the other PAD_PWR register located at 0x1A.
Description