a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 77

• Manufacturer Part Number: a2f500m3b-1csh484
• Description: Actel
• Manufacturer: Actel Corporation

Clock Conditioning Circuits
Table 2-83 • SmartFusion CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details
2. This delay is a function of voltage and temperature. See
3. T
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the
SmartFusion Microcontroller Subsystem User's
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
J
= 25°C, VCC = 1.5 V
CCC Electrical Specifications
Timing Characteristics
4
2,3
CCC_OUT
IN_CCC
2,3
2,3
OUT_CCC
Guide.
2, 3
Table 2-7 on page 2-9
R e v i s i o n 3
Minimum
1 Global
Network
0.50%
1.00%
1.75%
2.50%
0.025
Used
0.75
48.5
1.5
0.6
Actel SmartFusion Intelligent Mixed Signal FPGAs
Max Peak-to-Peak Period Jitter
Typical
for deratings.
160
2.2
Maximum
Networks
3 Global
0.70%
1.20%
2.00%
5.60%
Used
350
5.15
5.56
5.56
350
300
1.5
6.0
1.6
0.8
32
1
Units
MHz
MHz
ms
ps
ns
µs
ns
ns
ns
ns
ns
%
2- 65