a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 17
a2f500m3b-1csh484
Manufacturer Part Number
a2f500m3b-1csh484
Description
Actel
Manufacturer
Actel Corporation
Datasheet
1.A2F500M3B-1CSH484.pdf
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VCCxxxxIOBx Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the
following:
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLx exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the
information on clock and lock recovery.
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation
3. Chip is in the SoC Mode.
•
•
1. Core
2. Input buffers
During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
R e v i s i o n 3
Actel SmartFusion Intelligent Mixed Signal FPGAs
ProASIC3 FPGA Fabric User’s Guide
Figure 2-1 on page 2-6
2 -5
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