a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet
a2f500m3b-1csh484
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a2f500m3b-1csh484 Summary of contents
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... Variable Aspect Ratio 4,608-Bit SRAM Blocks – x1, x2, x4, x9, and x18 Organizations – True Dual-Port SRAM (excluding x18) 1 Theoretical maximum 2 A2F200 and larger devices September 2010 © 2010 Actel Corporation – Programmable Embedded FIFO Control Logic • Secure ISP with 128-Bit AES via JTAG • FlashLock • ...
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Actel’s SmartFusion Intelligent Mixed Signal FPGAs SmartFusion Family Product Table SmartFusion Device FPGA Fabric System Gates Tiles (D-flip-flops) RAM Blocks (4,608 bits) Microcontroller Flash (Kbytes) Subsystem (MSS) SRAM (Kbytes) Cortex-M3 with memory protection unit (MPU) 10/100 Ethernet MAC External Memory ...
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Package I/Os: MSS + FPGA I/Os Device A2F060 Package FG256 Direct Analog Input 6 Total Analog Input 10 Total Analog Output 1 1,2 MSS I/Os 25 FPGA I/Os 66 Total I/Os 102 Notes MSS I/Os are multiplexed and ...
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Actel’s SmartFusion Intelligent Mixed Signal FPGAs SmartFusion Block Diagram Supervisor PLL OSC RC + WDT 32 KHz RTC – APB SPI 1 UART 1 EFROM PDMA IAP SCB Volt Mon. Temp. (ABPS) ...
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SmartFusion System Architecture ISP AES Decryption Cortex-M3 Microcontroller Subsystem (MSS) SCB Note: Architecture for A2F500 Bank 0 Embedded FlashROM (eFROM) SCB ADC and DAC ADC and DAC Bank 3 Osc. CCC MSS FPGA PLL/CCC Revision 3 Actel SmartFusion Intelligent Mixed ...
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Actel’s SmartFusion Intelligent Mixed Signal FPGAs Product Ordering Codes _ A2F200 Blank eNVM Size Kbytes Kbytes Kbytes Kbytes E = 128 Kbytes F = 256 ...
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Table of Contents SmartFusion Device Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SmartFusion Device Family Overview Introduction The Actel SmartFusion™ family of intelligent mixed signal FPGAs builds on the technology first introduced with the Fusion mixed signal FPGAs. SmartFusion devices are made possible by integrating FPGA technology with programmable high-performance ...
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SmartFusion Device Family Overview ProASIC3 FPGA Fabric The Actel SmartFusion family, based on the proven, low power, firm-error immune ProASIC FPGA architecture, benefits from the advantages only flash-based devices offer: Reduced Cost of Ownership Advantages to the designer extend beyond ...
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PCB design. Flash-based SmartFusion devices simplify total system design and reduce cost and design risk, while increasing system reliability. Immunity to Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, ...
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SmartFusion DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond the operating conditions listed in device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional ...
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SmartFusion DC and Switching Characteristics Table 2-2 • Analog Maximum Ratings Parameter ABPS[n] pad voltage (relative to ground) GDEC[1: (±15.36 V range) CM[n] pad voltage relative to ground) TM[n] pad voltage (relative to ground) ADC[n] pad voltage (relative ...
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Table 2-3 • Recommended Operating Conditions Symbol T Junction temperature J 2 VCC 1 core supply voltage VJTAG JTAG DC voltage VPP Programming voltage VCCPLLx Analog power supply (PLL) VCCFPGAIOBx/ 1 supply voltage 4 VCCMSSIOBx 1.8 ...
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SmartFusion DC and Switching Characteristics Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits Product Grade Storage Temperature Commercial Min 0°C J Min 85°C J Industrial Min –40°C J Min. T ...
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Chip is in the SoC Mode. VCCxxxxIOBx Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V ...
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SmartFusion DC and Switching Characteristics VCC = VCCxxxxIOBx + VT where VT can be from 0. 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.425 V Activation trip ...
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Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature ...
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SmartFusion DC and Switching Characteristics Theta-JA Junction-to-ambient thermal resistance (θ JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package ...
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The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance requirement can be estimated by ...
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SmartFusion DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-8 • Quiescent Supply Current Characteristics Modes and Power Supplies 1 Power-down 0 V 1,2 Sleep 0 V Time Keeping mode Standby mode On Parameter ...
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Power-Down and Sleep Mode Implementation VJTAG and VPP should be connected to ground during Power-Down and Sleep modes. Note that when VJTAG is not powered, the 1.5 V voltage regulator cannot be enabled through TRSTB. VPP and VJTAG can be ...
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SmartFusion DC and Switching Characteristics Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS / 3.3 V ...
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Power Consumption of Various Internal Resources Table 2-13 • Different Components Contributing to Dynamic Power Consumption in SmartFusion Devices Parameter Definition PAC1 Clock contribution of a Global Rib PAC2 Clock contribution of a Global Spine PAC3 Clock contribution of a ...
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SmartFusion DC and Switching Characteristics Table 2-13 • Different Components Contributing to Dynamic Power Consumption in SmartFusion Devices Parameter Definition PAC24 Current Monitor Power Contribution PAC25 ABPS Power Contribution PAC26 Sigma-Delta DAC Power Contribution PAC27 Comparator Power Contribution PAC28 Voltage ...
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Table 2-14 • Different Components Contributing to the Static Power Consumption in SmartFusion Devices Parameter Definition PDC1 Core static power contribution PDC2 Device static power contribution in Standby Mode PDC3 Device static power contribution in Time Keeping mode PDC4 eNVM ...
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SmartFusion DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation ...
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Standby Mode DYN RC-OSC LPXTAL-OSC Time Keeping Mode DYN LPXTAL-OSC Global Clock Dynamic Contribution—P SoC Mode CLOCK AC1 SPINE AC2 N is the ...
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SmartFusion DC and Switching Characteristics Standby Mode and Time Keeping Mode NET I/O Input Buffer Dynamic Contribution—P SoC Mode INPUTS INPUTS Where the number of I/O input buffers used in the ...
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PLL Embedded Nonvolatile Memory Dynamic Contribution—P SoC Mode The eNVM dynamic power consumption is a piecewise linear function of frequency. β eNVM eNVM-BLOCKS 4 AC15 β ...
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SmartFusion DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.27 ns ISUD Input LVTTL Clock Register Cell t = 0.78 ...
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SmartFusion DC and Switching Characteristics t PY PAD DIN V PAD Y GND DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example CLK I/O Interface = MAX(t (R), t (F)) ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example) Actel SmartFusion Intelligent Mixed Signal FPGAs t DP DOUT t = MAX(t (R ...
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SmartFusion DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip VOL D 50 EOUT (R) VCC 50% EOUT ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial Conditions—Software Default Settings Applicable to FPGA I/O ...
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SmartFusion DC and Switching Characteristics Table 2-20 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial Conditions in all I/O Bank Types DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V ...
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Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx (per standard) Applicable to FPGA I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 3.3 V LVCMOS 2.5 V ...
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SmartFusion DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-25 • Input Capacitance Symbol C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-26 • I/O Output Buffer Maximum Resistances Applicable to FPGA I/O Banks ...
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Table 2-27 • I/O Output Buffer Maximum Resistances Applicable to MSS I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. These maximum values are provided for informational reasons ...
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SmartFusion DC and Switching Characteristics Table 2-29 • I/O Short Currents I Applicable to FPGA I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Note 85°C. ...
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The length of time an I/O can withstand I reliability data below is based I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition ...
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SmartFusion DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 ...
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Timing Characteristics Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks Drive Speed Strength Grade t t DOUT –1 0.50 ...
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SmartFusion DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...
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Timing Characteristics Table 2-43 • 2.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 2.3 V Applicable to FPGA I/O Banks Drive Speed Strength Grade DOUT –1 0.46 6.65 0.03 8 ...
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SmartFusion DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. ...
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Timing Characteristics Table 2-49 • 1.8 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 1.7 V Applicable to FPGA I/O Banks Drive Speed Strength Grade DOUT –1 0.50 9.10 0.03 4 ...
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SmartFusion DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...
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Timing Characteristics Table 2-55 • 1.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 1.425 V Applicable to FPGA I/O Banks Drive Speed Strength Grade t t DOUT –1 0.50 6. –1 ...
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SmartFusion DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-58 • Minimum and Maximum DC Input and Output Levels ...
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Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with ...
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SmartFusion DC and Switching Characteristics Table 2-62 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter VCCFPGAIOBx Supply voltage VOL Output low voltage VOH Output high voltage 1 I Output lower current Output high ...
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B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive ...
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SmartFusion DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-15 • Timing ...
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SmartFusion DC and Switching Characteristics Table 2-68 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-16 • Timing Model of ...
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SmartFusion DC and Switching Characteristics Table 2-69 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-17 • Input Register Timing Diagram Timing Characteristics Table 2-70 • Input Data Register Propagation Delays Worst Commercial-Case Conditions: T ...
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SmartFusion DC and Switching Characteristics Output Register 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-18 • Output Register Timing Diagram Timing Characteristics Table 2-71 • Output Data Register Propagation Delays Worst Commercial-Case ...
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Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-19 • Output Enable Register Timing Diagram Actel SmartFusion Intelligent Mixed Signal FPGAs 50% 50% t OEHD 50% ...
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SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-72 • Output Enable Register Propagation Delays Worst Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD t Data ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-20 • Input DDR Timing Model Table 2-73 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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SmartFusion DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-21 • Input DDR Timing Diagram Timing Characteristics Table 2-74 • Input DDR Propagation Delays Worst Commercial-Case Conditions: T Parameter t ...
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Output DDR Module A Data_F (from core) B CLK CLKBUF C D Data_R (from core) B CLR INBUF C Figure 2-22 • Output DDR Timing Model Table 2-75 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out DDROCLKQ t Asynchronous ...
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SmartFusion DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-23 • Output DDR Timing Diagram Timing Characteristics Table 2-76 • Output DDR Propagation Delays Worst Commercial-Case Conditions: T ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the ProASIC3/E, and SmartFusion ...
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SmartFusion DC and Switching Characteristics OUT GND VCC OUT Figure 2-25 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX PD(FF) applicable for the particular ...
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Timing Characteristics Table 2-77 • Combinatorial Cell Propagation Delays Worst Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 NAND2 Y = !(A · B) OR2 NOR2 XOR2 ...
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SmartFusion DC and Switching Characteristics 50% CLK 50% Data EN 50 PRE SUE CLR Out Figure 2-27 • Timing Model and Waveforms Timing Characteristics Table 2-78 • Register Delays Worst Commercial-Case Conditions: T Parameter t Clock-to-Q of ...
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Global Resource Characteristics A2F200 Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2-28 is used to drive all D-flip-flops in the device. CCC Figure 2-28 • Example of Global Tree Use in an A2F200 Device for ...
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SmartFusion DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...
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RC Oscillator The table below describes the electrical characteristics of the RC oscillator. RC Oscillator Characteristics Table 2-80 • Electrical Characteristics of the RC Oscillator Parameter Description FRC Operating frequency Accuracy Output jitter Output duty cycle IDYNRC Operating current Actel ...
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SmartFusion DC and Switching Characteristics Main and Lower Power Crystal Oscillator The tables below describes the electrical characteristics of the main and low power crystal oscillator. Table 2-81 • Electrical Characteristics of the Main Crystal Oscillator Parameter Description Operating frequency ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-83 • SmartFusion CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each Programmable ...
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SmartFusion DC and Switching Characteristics Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-29 • Peak-to-Peak Jitter Definition period_max period_min = T – T peak-to-peak period_max period_min R e visio ...
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FPGA Fabric SRAM and FIFO Characteristics FPGA Fabric SRAM ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB Figure 2-30 • RAM Models ...
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SmartFusion DC and Switching Characteristics Timing Waveforms CLK ADD t BKS BLK_B t ENS WEN_B Figure 2-31 • RAM Read for Pass-Through Output CLK ADD t BKS BLK_B t ENS WEN_B ...
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CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-33 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ...
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SmartFusion DC and Switching Characteristics CLK RESET_B Figure 2-35 • RAM Reset CYC t t CKH CKL visio RSTBQ ...
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Timing Characteristics Table 2-84 • RAM4K9 Worst Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup time BKS t BLK_B ...
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SmartFusion DC and Switching Characteristics Table 2-85 • RAM512X18 Worst Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) ...
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FIFO RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE Figure 2-36 • FIFO Model Actel SmartFusion Intelligent Mixed Signal FPGAs FIFO4K18 RD17 RD16 RD0 ...
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SmartFusion DC and Switching Characteristics Timing Waveforms RCLK/ WCLK RESET_B EMPTY AEMPTY FULL AFULL WA/RA (Address Counter) Figure 2-37 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-38 • FIFO EMPTY Flag and AEMPTY Flag Assertion ...
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WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-39 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY Figure 2-40 • FIFO EMPTY ...
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SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-86 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...
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Embedded Nonvolatile Memory Block (eNVM) Electrical Characteristics Table 2-87 describes the eNVM maximum performance. Table 2-87 • eNVM Block Timing, Worst Commercial Case Conditions: T Parameter t Maximum frequency for clock for the control logic – 6 cycles FMAXCLKeNVM (6:1:1:1*) ...
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SmartFusion DC and Switching Characteristics Table 2-89 • JTAG 1532 Worst Commercial-Case Conditions: T Parameter t ResetB Removal Time TRSTREM t ResetB Recovery Time TRSTREC t ResetB Minimum Pulse TRSTMPW Note: For specific junction temperature and voltage supply levels, refer ...
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Programmable Analog Specifications Current Monitor Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and 91 Ksps, after ...
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SmartFusion DC and Switching Characteristics Temperature Monitor Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages, with the output measured using the internal voltage reference ...
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Temperature Error Versus External Capacitance 1.00E -06 1.00E -05 Figure 2-42 • Temperature Error Versus External Capacitance Analog-to-Digital Converter (ADC) Unless otherwise noted, ADC direct input performance is specified at 25°C ...
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SmartFusion DC and Switching Characteristics Table 2-92 • ADC Specifications (continued) Specification Full power bandwidth Analog settling time Input capacitance Input resistance Input leakage current 2 Power supply rejection ratio ADC power supply operational current requirements Note: All 3.3 V ...
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Analog Bipolar Prescaler (ABPS) With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15. +15. scaled and offset by the ABPS input amplifier to match the ...
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SmartFusion DC and Switching Characteristics Table 2-93 • ABPS Performance Specifications (continued) Specification Power supply rejection ratio ABPS power supply current requirements (not including ADC or VAREFx) Comparator Unless otherwise specified, performance is specified at 25°C with nominal power supply ...
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Analog Sigma-Delta Digital to Analog Converter (DAC) Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator inputs updated at a 100 ...
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SmartFusion DC and Switching Characteristics 220 200 180 160 140 120 100 Figure 2-44 • Sigma-Delta DAC Setting Time 2- 86 Sigma Delta DAC Settling Time ...
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Voltage Regulator Table 2-96 • Voltage Regulator Symbol Parameter V Output voltage T = 25°C OUT J V Output offset voltage T = 25° ICC33A Operation current T = 25°C J ΔV Load regulation T = 25°C OUT ...
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SmartFusion DC and Switching Characteristics 0.015 0.01 0.005 0 -0.005 -0.01 -0.015 -0.02 -0.025 -40 Figure 2-45 • Typical Output Voltage -10 Figure 2-46 • Load Regulation 2- 88 Typical ...
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Serial Peripheral Interface (SPI) Characteristics This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given for load on the pins and all sequential timing characteristics are related to SPI_x_CLK. ...
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SmartFusion DC and Switching Characteristics Table 2-97 • SPI Characteristics Commercial Case Conditions: T Symbol Description and Condition sp6 Data from master (SPI_x_DO) setup time sp7 Data from master (SPI_x_DO) hold time 2 sp8 SPI_x_DI setup time 2 sp9 SPI_x_DI ...
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Inter-Integrated Circuit (I This section describes the DC and switching of the I characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer page 2-92. 2 Table 2-98 • ...
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Table 2-98 • Characteristics Commercial Case Conditions: T Parameter Definition 3 t STOP setup time SU;STO t Maximum spike width filtered FILT Notes: 1. These maximum values are provided for information only. Minimum output buffer resistance values ...
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SmartFusion Development Tools SmartFusion™ applications will be developed by a multi-discipline team of designers working on one project or one designer acting in several roles. Actel has developed design tools and flows to meet the needs of three ...
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SmartFusion Development Tools The MSS configurator includes the following: • A simple configurator for the embedded designer to control the MSS peripherals and I/Os • A method to import and view a hardware configuration from the FPGA flow into the ...
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Software Integrated Design Environment (IDE) Choices Software IDE www.actel.com Website Free with Libero IDE Free versions from Actel Available from Vendor Compiler Debugger Instruction Set Simulator Debug Hardware Operating System and Middleware Support Micrium is recognized as a leader in ...
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SmartFusion Programming SmartFusion devices have three separate flash areas that can be programmed: 1. The FPGA fabric 2. The embedded nonvolatile memories (eNVMs) 3. The embedded flash ROM (eFROM) There are essentially three methodologies for programming these areas: ...
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SmartFusion Programming Note: Standard ARM JTAG connectors do not have access to the JTAGSEL pin. Actel’s free Eclipse- based IDE, Soft Console, automatically sets JTAGSEL via FlashPro4 to the appropriate state for programming all memory regions. VJTAG (1 ...
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Re-Programming the eNVM Blocks Using the Cortex-M3 In this mode the Cortex-M3 is executing the eNVM programming algorithm from eSRAM. Since individual pages (132 bytes) of the eNVM can be write-protected, the programming algorithm software can be protected from inadvertent ...
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Pin Descriptions Supply Pins Name Type GND Ground Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs GND15ADC0 Ground Quiet analog ground to the 1.5 V circuitry of the first analog-to-digital converter (ADC) GND15ADC1 Ground Quiet analog ...
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Pin Descriptions Name Type VCC15A Supply Clean analog 1.5 V supply to the analog circuitry VCC15ADC0 Supply Analog 1.5 V supply to the first ADC VCC15ADC1 Supply Analog 1.5 V supply to the second ADC VCC15ADC2 Supply Analog 1.5 V ...
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Name Type VCCMSSIOB2 Supply Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the output buffers and I/O logic VCCMSSIOB4 Supply Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for ...
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Pin Descriptions User-Defined Supply Pins Polarity/Bus Name Type Size VAREF0 Input 1 VAREF1 Input 1 VAREF2 Input 1 VAREFOUT Out Description Analog reference voltage for first ADC The SmartFusion device can be configured to generate a ...
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User Pins Name Type Polarity/Bus Size GPIO_x In/out 32 IO In/out Actel SmartFusion Intelligent Mixed Signal FPGAs Description Microcontroller Subsystem (MSS) General Purpose I/O (GPIO). The MSS GPIO pin functions as an input, output, tristate, or bidirectional buffer with configurable ...
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Pin Descriptions Special Function Pins Name Type Polarity/Bus Size NC DC LPXIN In LPXOUT In MAINXIN In MAINXOUT Out NCAP connect This pin is not connected to circuitry within the device. These pins can be driven ...
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Name Type Polarity/Bus Size PCAP 1 PTBASE 1 PTEM 1 MSS_RESET_N In Low PU_N In Low Actel SmartFusion Intelligent Mixed Signal FPGAs Description Positive Capacitor connection. This is the positive terminal of the charge pump. A capacitor, with a 2.2 ...
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Pin Descriptions JTAG Pins SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1 3.3 V (nominal). VCC must also be powered for the JTAG state ...
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Table 5-1 • Recommended Tie-Off Values for the TCK and TRST Pins V JTAG V at 3.3 V JTAG V at 2.5 V JTAG V at 1.8 V JTAG V at 1.5 V JTAG Notes: 1. The TCK pin can ...
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Pin Descriptions Microcontroller Subsystem (MSS) Polarity/ Name Type Bus Size External Memory Controller EMC_ABx Out EMC_BYTENx Out LOW/2 EMC_CLK Out EMC_CSx_N Out LOW/2 EMC_DBx In/out EMC_OENx_N Out LOW/2 EMC_RW_N Out 2 Inter-Integrated Circuit (I C) Peripherals I2C_0_SCL In/out I2C_0_SDA In/out ...
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Polarity/ Name Type Bus Size SPI_1_DO Out 1 SPI_1_SS Out 1 Universal Asynchronous Receiver/Transmitter (UART) Peripherals UART_0_RXD In 1 UART_0_TXD Out 1 UART_1_RXD In 1 UART_1_TXD Out 1 Ethernet MAC MAC_CLK In Rise MAC_CRSDV In High MAC_MDC Out Rise MAC_MDIO ...
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Pin Descriptions Analog Front-End (AFE) Name Type ABPS0 In SCB 0 / active bipolar prescaler input 1. See the Active Bipolar Prescaler (ABPS) section in the Programmable Analog User’s ABPS1 In SCB 0 / active bipolar prescaler Input 2 ABPS2 ...
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Name Type TM1 In SCB 1 / low side of current monitor / comparator. Negative input / high side of temperature monitor. TM2 In SCB 2 / low side of current monitor / comparator. Negative input / high side of ...
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Pin Descriptions Analog Front-End Pin-Level Function Multiplexing Table 5-2 describes the relationships between the various internal signals found in the analog front-end (AFE) and how they are multiplexed onto the external package pins. Note that, in general, only one function ...
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Table 5-2 • Relationships Between Signals in the Analog Front-End ADC Dir.-In Pin Channel Option Prescaler SDD2 ADC2_CH15 TM0 ADC0_CH4 Yes TM1 ADC0_CH8 Yes TM2 ADC1_CH4 Yes TM3 ADC1_CH8 Yes TM4 ADC2_CH4 Yes Notes: 1. ABPSx_IN: Input to active bipolar ...
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Pin Descriptions Pin Assignment Tables 288-Pin CSP Note: Bottom view For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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Pin Number A2F200 Function A1 VCCFPGAIOB0 A2 GNDQ A3 EMC_CLK/GAA0/IO00NDB0V0 A4 EMC_RW_N/GAA1/IO00PDB0V0 A5 GND A6 EMC_CS1_N/GAB1/IO01PDB0V0 A7 EMC_CS0_N/GAB0/IO01NDB0V0 A8 EMC_AB[0]/IO04NPB0V0 A9 VCCFPGAIOB0 A10 EMC_AB[4]/IO06NDB0V0 A11 EMC_AB[8]/IO08NPB0V0 A12 EMC_AB[14]/IO11NPB0V0 A13 GND A14 EMC_AB[18]/IO13NDB0V0 A15 EMC_AB[24]/IO16NDB0V0 A16 EMC_AB[25]/IO16PDB0V0 A17 VCCFPGAIOB0 A18 EMC_AB[20]/IO14NDB0V0 ...
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Pin Descriptions Pin Number AA16 AA17 AA18 AA19 AA20 AA21 B1 B21 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C21 D1 D3 D19 D21 EMC_BYTEN[0]/GAC0/IO02NDB0V0 ...
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Pin Number A2F200 Function E8 EMC_OEN1_N/IO03PDB0V0 E9 EMC_AB[3]/IO05PDB0V0 E10 EMC_AB[10]/IO09NDB0V0 E11 EMC_AB[7]/IO07PDB0V0 E12 EMC_AB[13]/IO10PDB0V0 E13 EMC_AB[16]/IO12NDB0V0 E14 EMC_AB[17]/IO12PDB0V0 E15 GCB0/IO27NDB1V0 E16 GCB1/IO27PDB1V0 E17 GCB2/IO24PDB1V0 E19 GCA0/IO28NDB1V0 E21 GCA1/IO28PDB1V0 F1 VCCFPGAIOB5 F3 GFB2/IO68NDB5V0 F5 GFA2/IO68PDB5V0 F6 EMC_DB[11]/IO69PDB5V0 F7 GND F8 GFC1/IO66PPB5V0 ...
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Pin Descriptions Pin Number G17 G19 G21 H10 H11 H12 H13 H14 H16 H17 H19 H21 J10 J11 J12 J13 J14 J15 J16 J17 J19 J21 K1 ...
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Pin Number A2F200 Function K3 EMC_DB[5]/GEA1/IO61PPB5V0 K5 EMC_DB[0]/GEA2/IO59NDB5V0 K6 EMC_DB[3]/GEC2/IO60PPB5V0 K8 GND K9 VCC K10 GND K11 VCC K12 GND K13 VCC K14 GND K16 LPXOUT K17 GNDLPXTAL K19 GNDMAINXTAL K21 MAINXIN L1 GNDRCOSC L3 VCCFPGAIOB5 L5 EMC_DB[2]/IO60NPB5V0 L6 GNDQ ...
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Pin Descriptions Pin Number M12 M13 M14 M16 M17 M19 M21 N10 N11 N12 N13 N14 N15 N16 N17 N19 N21 P10 P11 P12 P13 P14 P16 ...
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Pin Number A2F200 Function P17 I2C_0_SCL/GPIO_23 P19 VCCMSSIOB2 P21 GND R1 MAC_MDIO/IO49RSB4V0 R3 MAC_TXEN/IO52RSB4V0 R5 MAC_TXD[0]/IO56RSB4V0 R6 MAC_CRSDV/IO51RSB4V0 R9 GNDA R13 GNDA R16 UART_1_RXD/GPIO_29 R17 UART_1_TXD/GPIO_28 R19 I2C_0_SDA/GPIO_22 R21 I2C_1_SDA/GPIO_30 T1 GND T3 MAC_TXD[1]/IO55RSB4V0 T5 MAC_RXD[1]/IO53RSB4V0 T6 MAC_RXER/IO50RSB4V0 T7 CM1 ...
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Pin Descriptions Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U19 U21 V1 V3 V19 V21 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W21 Y1 Y21 ...
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FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. . Actel SmartFusion Intelligent Mixed Signal FPGAs A1 Ball Pad Corner ...
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Pin Descriptions Pin Number A2F200 Function A1 GND A2 VCCFPGAIOB0 A3 EMC_AB[0]/IO04NDB0V0 A4 EMC_AB[1]/IO04PDB0V0 A5 GND A6 EMC_AB[3]/IO05PDB0V0 A7 EMC_AB[5]/IO06PDB0V0 A8 VCCFPGAIOB0 A9 GND A10 EMC_AB[14]/IO11NDB0V0 A11 EMC_AB[15]/IO11PDB0V0 A12 GND A13 EMC_AB[20]/IO14NDB0V0 A14 EMC_AB[24]/IO16NDB0V0 A15 VCCFPGAIOB0 A16 GND B1 EMC_DB[15]/GAA2/IO71PDB5V0 ...
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Pin Number A2F200 Function C1 EMC_DB[14]/GAB2/IO71NDB5V0 C2 VCCPLL C3 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0 C4 VCCFPGAIOB0 C5 EMC_CS0_N/GAB0/IO01NDB0V0 C6 EMC_CS1_N/GAB1/IO01PDB0V0 C7 GND C8 EMC_AB[8]/IO08NDB0V0 C9 EMC_AB[11]/IO09PDB0V0 C10 VCCFPGAIOB0 C11 EMC_AB[17]/IO12PDB0V0 C12 EMC_AB[19]/IO13PDB0V0 C13 GND C14 GBA2/IO20PPB1V0 C15 GCA2/IO23PDB1V0 C16 IO23NDB1V0 D1 VCCFPGAIOB5 D2 ...
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Pin Descriptions Pin Number A2F200 Function D16 VCCFPGAIOB1 E1 EMC_DB[13]/GAC2/IO70PDB5V0 E2 EMC_DB[12]/IO70NDB5V0 E3 GFA2/IO68PDB5V0 E4 EMC_DB[10]/IO69NPB5V0 E5 GNDQ E6 GND E7 VCCFPGAIOB0 E8 GND E9 VCCFPGAIOB0 E10 GND E11 VCCFPGAIOB0 E12 GCA1/IO28PDB1V0 E13 VCCFPGAIOB1 E14 GCB1/IO27PDB1V0 E15 GDC1/IO29PDB1V0 E16 GDC0/IO29NDB1V0 ...
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Pin Number A2F200 Function F13 GNDQ F14 GCB0/IO27NDB1V0 F15 GND F16 VCCENVM G1 EMC_DB[8]/GEC0/IO63NDB5V0 G2 EMC_DB[7]/GEB1/IO62PDB5V0 G3 EMC_DB[6]/GEB0/IO62NDB5V0 G4 GFC2/IO67PDB5V0 G5 IO67NDB5V0 G6 GND G7 VCC G8 GND G9 VCC G10 GND G11 VCCFPGAIOB1 G12 VPP G13 TRSTB G14 TMS ...
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Pin Descriptions Pin Number A2F200 Function H12 VJTAG H13 TDO H14 TDI H15 JTAGSEL H16 GND J1 EMC_DB[4]/GEA0/IO61NPB5V0 J2 EMC_DB[3]/GEC2/IO60PDB5V0 J3 EMC_DB[2]/IO60NDB5V0 J4 GNDRCOSC J5 GNDQ J6 GND J7 VCC J8 GND J9 VCC J10 GND J11 VCCMSSIOB2 J12 I2C_0_SCL/GPIO_23 ...
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Pin Number A2F200 Function K10 VCC K11 GND K12 UART_0_RXD/GPIO_21 K13 GND K14 UART_1_TXD/GPIO_28 K15 UART_1_RXD/GPIO_29 K16 UART_0_TXD/GPIO_20 L1 GND L2 MAC_TXEN/IO52RSB4V0 L3 MAC_CRSDV/IO51RSB4V0 L4 MAC_RXER/IO50RSB4V0 L5 MAC_CLK L6 GND L7 VCC L8 GND L9 VCC L10 GND L11 VCCMSSIOB2 ...
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Pin Descriptions Pin Number A2F200 Function M11 TM2 M12 CM2 M13 SPI_0_SS/GPIO_19 M14 VCCMSSIOB2 M15 SPI_0_CLK/GPIO_18 M16 SPI_0_DI/GPIO_17 N1 MAC_RXD[1]/IO53RSB4V0 N2 VCCMSSIOB4 N3 VCC15A N4 VCC33AP N5 ABPS3 N6 TM1 N7 GND33ADC0 N8 VCC33ADC1 N9 ADC5 N10 CM3 N11 GNDAQ ...
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Pin Number A2F200 Function P8 VCC15ADC0 P9 ADC6 P10 TM3 P11 GNDA P12 VCCMAINXTAL P13 GNDLPXTAL P14 VDDBAT P15 PTEM P16 PTBASE R1 PCAP R2 SDD0 R3 ABPS0 R4 TM0 R5 ABPS2 R6 ADC1 R7 VCC33ADC0 R8 VCC15ADC1 R9 ADC7 ...
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Pin Descriptions Pin Number A2F200 Function T9 VAREF1 T10 ABPS6 T11 ABPS5 T12 SDD1 T13 GNDVAREF T14 GNDMAINXTAL T15 VCCLPXTAL T16 PU_N Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the ...
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FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Actel SmartFusion Intelligent Mixed Signal FPGAs A1 Ball Pad Corner ...
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Pin Descriptions Pin Number A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 ...
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Pin Number A2F200 Function AA15 AA16 MAINXIN AA17 MAINXOUT AA18 LPXIN AA19 LPXOUT AA20 AA21 AA22 SPI_1_CLK/GPIO_26 AB1 AB2 GPIO_13/IO36RSB4V0 AB3 GPIO_14/IO35RSB4V0 AB4 AB5 AB6 AB7 ABPS3 AB8 AB9 GND15ADC0 AB10 VCC33ADC1 AB11 VAREF1 AB12 AB13 AB14 ABPS4 AB15 GNDAQ ...
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Pin Descriptions Pin Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 ...
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Pin Number A2F200 Function C21 GBC2/IO21PDB1V0 C22 GBB2/IO20NDB1V0 D1 D2 EMC_DB[12]/IO70NDB5V0 D3 EMC_DB[13]/GAC2/IO70PDB5V0 D10 EMC_OEN0_N/IO03NDB0V0 D11 EMC_AB[10]/IO09NDB0V0 D12 EMC_AB[11]/IO09PDB0V0 D13 EMC_AB[9]/IO08PDB0V0 D14 D15 GBC1/IO17PPB0V0 D16 EMC_AB[25]/IO16PDB0V0 D17 D18 GBA1/IO19PPB0V0 D19 D20 D21 IO21NDB1V0 D22 ...
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Pin Descriptions Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 ...
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Pin Number A2F200 Function G5 EMC_DB[11]/IO69PPB5V0 G6 GNDQ VCCFPGAIOB0 G10 G11 VCCFPGAIOB0 G12 G13 VCCFPGAIOB0 G14 G15 VCCFPGAIOB0 G16 GNDQ G17 G18 G19 GCA2/IO23PDB1V0 G20 IO24NDB1V0 G21 GCB2/IO24PDB1V0 G22 H1 EMC_DB[7]/GEB1/IO62PDB5V0 H2 VCCFPGAIOB5 H3 EMC_DB[8]/GEC0/IO63NDB5V0 H4 H5 ...
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Pin Descriptions Pin Number H19 H20 H21 H22 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K10 ...
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Pin Number A2F200 Function K11 K12 K13 K14 K15 K16 VCCFPGAIOB1 K17 K18 GDA1/IO31PDB1V0 K19 GDA0/IO31NDB1V0 K20 GDC1/IO29PDB1V0 K21 GDC0/IO29NDB1V0 K22 VCCFPGAIOB5 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 GNDQ ...
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Pin Descriptions Pin Number M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N10 N11 N12 N13 N14 N15 N16 ...
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Pin Number A2F200 Function N17 N18 VCCFPGAIOB1 N19 VCCENVM N20 GNDENVM N21 N22 GNDRCOSC P10 P11 P12 P13 P14 P15 P16 VCCFPGAIOB1 P17 P18 P19 P20 P21 P22 TRSTB R1 MSS_RESET_N ...
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Pin Descriptions Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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Pin Number A2F200 Function U1 U2 GPIO_5/IO42RSB4V0 U3 GPIO_10/IO58RSB4V0 U4 VCCMSSIOB4 U5 MAC_RXD[1]/IO53RSB4V0 U6 U7 VCC33AP U8 VCC33N U9 U10 VAREF0 U11 GND33ADC1 U12 U13 U14 U15 GNDVAREF U16 VCC33SDD1 U17 SPI_0_DO/GPIO_16 U18 UART_0_RXD/GPIO_21 U19 VCCMSSIOB2 U20 I2C_1_SCL/GPIO_31 U21 I2C_0_SCL/GPIO_23 ...
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Pin Descriptions Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 ...
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Pin Number A2F200 Function Y7 Y8 GNDTM0 Y9 Y10 VCC15ADC0 Y11 ABPS7 Y12 Y13 Y14 Y15 Y16 VCCMAINXTAL Y17 Y18 Y19 VCC33A Y20 SPI_0_SS/GPIO_19 Y21 VCCMSSIOB2 Y22 UART_0_TXD/GPIO_20 Note: Shading denotes pins that do not have completely identical functions from ...
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Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the SmartFusion datasheet. Revision Revision 3 The "I/Os and Operating Voltage" section (September 2010) with on-chip 1.5 V regulator" and ...
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Revision Revision 3 The "Power-Down and Sleep Mode Implementation" section (continued) A note was added stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is out_CCC limited to 100 MHz (maximum) ...
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Revision Revision 2 The number of PLLs for A2F200 was changed from the (continued) Product Table" (SAR 25093). Values for direct analog input, total analog input, and total I/Os were updated for the FG256 package, A2F060, ...
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Revision Revision 0 Table 2-13 • Different Components Contributing to Dynamic Power Consumption in (continued) SmartFusion Devices Table 2-14 • Different Components Contributing to the Static Power Consumption in SmartFusion Devices The "Power Calculation Methodology" section Table 2-80 • Electrical ...
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Revision Draft B Table 2-8 • Quiescent Supply Current Characteristics (continued) Table 2-13 • Different Components Contributing to Dynamic Power Consumption in SmartFusion Devices Power Consumption in SmartFusion Devices Figure 2-3 • Timing Model The temperature associated with the reliability ...
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Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "SmartFusion Device Status" ...
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