A500K270 Actel Corporation, A500K270 Datasheet

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... Yes Yes Yes Yes 208 208 272 272, 456 144 144, 256 A500K270 475,000 215,000 26,880 54k 63k 24 28 26,880 4 4 362 440 Yes Yes Yes Yes 208 208 456 456 256 ...

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... A500K050 = 100,000 Equivalent System Gates A500K130 = 290,000 Equivalent System Gates A500K180 = 370,000 Equivalent System Gates A500K270 = 475,000 Equivalent System Gates Note: This family has been discontinued. 2 embedded two-port memory. These memory blocks include hardwired FIFO circuitry as well as circuits to generate or check parity. This minimizes external logic gate count and complexity while maximizing flexibility and utility ...

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... A500K180 Device 208-Pin Plastic Quad Flat Pack (PQFP) 256-Pin Plastic Ball Grid Array (PBGA) 456-Pin Plastic Ball Grid Array (PBGA) A500K270 Device 208-Pin Plastic Quad Flat Pack (PQFP) 256-Pin Plastic Ball Grid Array (PBGA) 456-Pin Plastic Ball Grid Array (PBGA) 676-Pin Fine Ball Grid Array (FBGA) Contact your Actel sales representative for package availability ...

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The ProASIC 500K family’s proprietary architecture provides granularity comparable to gate arrays. Unlike SRAM-based FPGAs that utilize look-up tables or ...

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Pr oAS Word Figure 2 • Flash Switch (CLK (Reset) Figure 3 • Core Logic Tile ...

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Figure 4 • Ultra Fast Local Resources 4 Tiles Long 2 Tiles Long Figure 5 • Efficient Long Line Resources Inputs ...

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Pr oAS Speed Very Long Line Resouces PAD RING Figure 6 • High Speed Very Long Line Resources Discontinued – v3.0 7 ...

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... Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map different internal/external clocks in an A500K270 device (Table 1). Global Pads PAD RING Figure 7 • ...

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... meet complex system design needs, the ProASIC 500K family offers devices with a large number of I/O pins 440 user I/O pins on the A500K270. If the I/O pad is powered at 3.3V, each I/O can be selectively configured at 2.5V and 3.3V threshold levels. Table 2 shows the available supply voltage configurations ...

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These pins are dedicated for boundary-scan test usage. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 11 ...

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... This provides 63k bits of wiring, physical total memory for two-port and single port usage in the A500K270 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports are not supported. Additional characteristics include programmable flags as well as parity check and generation ...

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... Synchronous Transparent FIFO Synchronous Synchronous Transparent FIFO Synchronous Synchronous Pipelined FIFO Synchronous Synchronous Pipelined 12 blocks of the A500K270 yield an effective 6,912 bits of multiple port memories. The ACTgen building wider and deeper memories for optimal memory usage. Parity Checked Generated Checked Generated Checked Generated ...

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Pr oAS <0:8> SRAM WADDR <0:7> (256 X 9) WRB Sync Write & WBLKB Sync Read Ports WCLKS WPE PARODD DI <0:8> SRAM WADDR <0:7> (256 X ...

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... Word 256 Depth Figure 14 • A500K270 Memory Block Architecture Word Width 9 Word 256 Depth 256 256 256 1,024 words x 9bits, 1 read, 1 write Figure 15 • Example Showing Memories with Different Widths and Depths Word Width 9 Word 256 Depth Read Ports 512 words x 9bits, 4 read, 1 write Figure 16 • ...

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... ACTgen allows any bit width up to 252 (for the A500K270 device). ACTgen also enables optimal memory stacking in 256-word increments. However, any word depth may be combined for up to 7,168 words. ACTgen allows the user to generate distributed memory. Place and route is performed by Actel’ ...

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The ProASIC 500K family is available in a number of package types. Actel has selected packages ...

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... The following is an example using a shift register design + P ios memory with 13,440 storage tiles and 0 logic tile. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz for a A500K270 MHz s = 13,440 => 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and MHz => ...

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Parameter Supply Voltage Core (V ) DDL ...

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Pr oAS ...

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Symbol Parameter V Supply Voltage DDP V Supply Voltage, Logic Array DDL Output High ...

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Pr oAS ...

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Symbol Parameter Switching Current High I OH(AC) (Test Point) Switching Current Low I OL(AC) ...

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Pr oAS Figure 18 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the ProASIC family. 150.0 100.0 50.0 0.0 0 0.5 ...

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Pr oAS ...

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Pr oAS ...

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Pr oAS Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RB=(RBD+RBLKB) RADDR DO RPE t RACS t RDCS ° ...

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Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RB=(RDB+RBLKB) New Valid RADDR Address DO RPE t RACS t RACH t RDCH t RDCS ° 0° ...

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Pr oAS Asynchronous RAM Write WADDR WB=(WRB+WBLKB) WPE ° 0° ...

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Asynchronous RAM Read, Address Controlled, RDB=0 RADDR ° 0° DDL Symbol t Description xxx ACYC Read cycle time OAA New ...

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Pr oAS Synchronous RAM Write WCLKS WRB, WBLKB WADDR, DI WPE t WRCH , t WBCH t WRCS , t WBCS t DCS , t WDCS t WPCH ...

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Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem ...

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Pr oAS FULL RB Write Write inhibited cycle WB Figure 19 • Write Timing Diagram EMPTY WB Read Read inhibited cycle RB Figure 20 • Read Timing Diagram ...

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Asynchronous FIFO Read RB=(RDB+RBLKB) DO RPE WB EMPTY FULL EQTH, GETH t RDWRS t RPRDH T = 0°C to 110° 2.3V to 2.7V J DDL Symbol t Description xxx ERDH, Old EMPTY, FULL, EQTH, & GETH valid hold ...

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Pr oAS Asynchronous FIFO Write WB=(WRB+WBLKB) DI WPE RB FULL EMPTY EQTH, GETH t WRRDS T = 0°C to 110° 2.3V to 2.7V DDL J Symbol ...

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Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RDB DO Old Data Out RPE EMPTY FULL EQTH, GETH t RDCH t RDCS t OCH t RPCH T = 0°C to 110° 2.3V to 2.7V J DDL ...

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Pr oAS Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RDB DO RPE EMPTY FULL EQTH, GETH t RDCH t RDCS T = 0°C to 110°C; V ...

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Synchronous FIFO Write WCLKS WRB, WBLKB DI WPE FULL EMPTY EQTH, GETH t WRCH , t WBCH t WRCS , t WBCS t DCS t WPCH t DCH T = 0°C to 110° 2.3V to 2.7V J DDL ...

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Pr oAS FIFO Reset RESETB WRB, WBLKB WCLKS, RCLKS FULL EMPTY EQTH, GETH t ERSA , t FRSA t THRSA ° ...

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I/O User Input/Output The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL specifications. Unused ...

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Pr oAS 208 ...

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... DDL DDL I/O I/O 89 I/O I/O 90 I/O I DDP DDP GND GND 93 I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 I/O I/O 101 I/O I/O 102 I/O I/O 103 GND GND 104 Discontinued – v3.0 ® Pr oAS A500K130 A500K180 A500K270 Function Function Function DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

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... GND 193 V V 194 DDL DDL I/O I/O 195 I/O I/O 196 I/O I/O 197 I/O I/O 198 I/O I/O 199 I/O I/O 200 I/O I/O 201 I/O I/O 202 I/O I/O 203 I/O I/O 204 I/O I/O 205 I/O I/O 206 I/O I/O 207 GND GND 208 Discontinued – v3.0 A500K130 A500K180 A500K270 Function Function Function DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP ...

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Pr oAS Pin A500K050 A500K130 Number Function Function A1 I/O I/O A2 I/O I/O A3 I/O I/O A4 I/O ...

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Pin A500K050 A500K130 Number Function Function L3 I/O I DDL DDL L9 GND GND L10 GND GND L11 GND GND L12 ...

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Pr oAS ...

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... AC20 I/O I/O AC21 TMS I/O AC22 TDO I/O AC23 V DDP I/O AC24 RCK V AC25 I/O DDL V AC26 NC DDL V AD1 NC DDL I/O AD2 I/O I/O AD3 V DDP I/O AD4 I/O Discontinued – v3.0 ® Pr oAS A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDL DDL V V DDL DDL V V DDL DDL I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

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... V DDP I/O AF26 V DDP I DDP I DDP I/O B3 I/O I/O B4 I/O I/O B5 I/O I/O B6 I/O I/O B7 I/O I/O B8 I/O I/O B9 I/O I/O B10 I/O I/O B11 I/O I/O B12 I/O I/O B13 I/O I/O B14 I/O I/O B15 I/O I/O B16 I/O V B17 I/O PN TRST B18 I/O Discontinued – v3.0 A500K180 A500K270 Function Function V V DDP DDP V V DDP DDP V V DDP DDP V V DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI TDI I/O I DDP ...

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... I/O I/O E20 V DDL I/O E21 V DDL I/O E22 V DDL I/O E23 I/O V E24 I/O DDP I/O E25 I/O I/O E26 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I DDL I/O F22 V DDL Discontinued – v3.0 ® Pr oAS A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDL DDL V V DDL DDL V V DDL ...

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... N3 I/O I/O N4 I/O I/O N5 I/O I/O N11 GND I/O N12 GND I/O N13 GND I/O N14 GND I/O N15 GND I/O N16 GND I/O N22 I/O I/O N23 GL I/O N24 I/O I/O N25 I/O I/O N26 I/O Discontinued – v3.0 A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O GND GND GND ...

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... W3 I/O I/O W4 I/O I DDL I/O W22 V DDL I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O W26 I/O I I/O Y2 I/O I/O Y3 I/O GND Y4 I/O GND Y5 V DDL GND Y22 V DDL GND Y23 I/O GND Y24 I/O GND Y25 I/O I/O Y26 NC Discontinued – v3.0 ® Pr oAS A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDL DDL ...

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Pr oAS (Continued ...

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Pin A500K050 A500K130 Number Function Function A1 I/O I/O A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 GND GND A7 I/O I DDL DDL ...

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Pr oAS Pin A500K050 A500K130 Number Function Function K1 I/O I/O K2 ...

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(Continued Ball Pad Corner 14 13 ...

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... D3 I/O I/O D4 I/O I/O D5 I/O I/O D6 I/O GND D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O D14 I/O I/O D15 I/O I/O D16 I/O I/O E1 I/O I/O E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I I/O E8 I/O I/O E9 I/O I/O E10 V I/O E11 V I/O E12 I/O I/O E13 I/O I/O E14 I/O Discontinued – v3.0 A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP V V DDP DDP DDP I/O I/O I/O I DDP DDP DDP V V DDP ...

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... K4 I I/O K7 GND GL K8 GND I/O K9 GND I/O K10 GND I/O K11 V I/O K12 V Discontinued – v3.0 ® Pr oAS A500K180 A500K270 Function Function V V DDL DDL DDL GND GND GND GND GND GND GND GND V V DDL DDL DDL I/O I/O I/O I/O I/O I/O I/O I ...

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... V P1 I/O DDL GND P2 I I/O DDP I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 I/O I/O P8 I/O I/O P9 I/O I/O P10 I/O I/O P11 I/O I/O P12 I/O V P13 TCK DDP V P14 V DDP I/O P15 TRST I/O P16 I I/O DDP V R2 I/O DDP I/O R3 I/O I/O R4 I/O I/O R5 I/O I/O R6 I/O I/O R7 I/O I/O R8 I/O I/O R9 I/O I/O R10 I/O Discontinued – v3.0 A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK TCK TRST TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 61 ...

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... GND GND T2 I/O I/O T3 I/O I/O T4 I/O I/O T5 I/O I/O 62 A500K270 Pin A500K130 Function Number Function I/O T6 I/O I/O T7 I/O I/O T8 I/O TDI T9 I/O V T10 I/O PN TDO T11 I/O GND T12 I/O I/O T13 I/O I/O T14 I/O I/O T15 TMS I/O T16 GND Discontinued – v3.0 ® Pr oAS A500K180 A500K270 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TMS GND GND ...

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Pr oAS (Continued ...

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... AD4 I/O I/O AD5 I/O I/O AD6 I/O TCK AD7 I/O TRST AD8 I/O I/O AD9 I/O I/O AD10 I/O Discontinued – v3.0 ® Pr oAS Pin A500K270 Pin A500K270 Number Function Number Function AD11 I/O AE23 AD12 I/O AE24 AD13 I/O AE25 AD14 I/O AE26 AD15 I/O AF1 AD16 I/O AF2 AD17 I/O AF3 AD18 ...

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... I/O F4 I/O I/O F5 GND I/O F6 I/O I I/O F8 I/O I/O F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O F13 I/O I/O F14 I/O I/O F15 I/O I/O F16 I/O I/O F17 I/O I/O F18 I/O Discontinued – v3.0 Pin A500K270 Pin A500K270 Number Function Number Function F19 I/O H5 F20 I/O H6 F21 I/O H7 F22 I/O H8 F23 I/O H9 F24 I/O H10 F25 I/O H11 F26 I/O H12 G1 I/O H13 G2 I/O H14 G3 I/O H15 G4 I/O H16 G5 I/O H17 G6 I/O H18 G7 I/O H19 ...

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... NC DDP V N21 I/O DDL GND N22 GL GND N23 I/O GND N24 I/O GND N25 GL GND N26 I/O Discontinued – v3.0 ® Pr oAS Pin A500K270 Pin A500K270 Number Function Number Function P1 GL R13 P2 I/O R14 P3 I/O R15 P4 I/O R16 P5 I/O R17 P6 I/O R18 P7 NC R19 P8 V R20 ...

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... DDL V W5 I/O DDL V W6 I/O DDL DDL DDL DDL DDL DDL DDP Discontinued – v3.0 Pin A500K270 Pin A500K270 Number Function Number Function W10 V Y5 DDP W11 V Y6 DDP W12 V Y7 DDP W13 V Y8 DDP W14 V Y9 DDP W15 V Y10 ...

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... MHz)” on page 26 J “Global Input Buffer Delays (Worst-Case Commercial = 3.0V 2.3V 70°C, fCLOCK = 250 MHz)” on page 27 DDL J for A500K050 is new. for A500K130 and A500K270 are Discontinued – v3.0 ® Pr oAS Page page 3 page 3 page 13 ...

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Pr oAS order to provide the latest information to designers, some ...

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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 http://www.actel.com Actel Corporation ...