a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 32

• Manufacturer Part Number: a2f500m3b-1csh484
• Description: Actel
• Manufacturer: Actel Corporation

SmartFusion DC and Switching Characteristics
2- 20
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some
examples:
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
non-tristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component
α
α
Component
β
β
β
β
1
2
3
4
1
2
•
•
The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the
clock frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
– …
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
I/O output buffer enable rate
FPGA fabric SRAM enable rate for read
operations
FPGA fabric SRAM enable rate for write
operations
eNVM enable rate for read operations
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Definition
R e visio n 3
Definition
Toggle rate of the logic driving the
output buffer
Guideline
12.5%
12.5%
< 5%
Guideline
10%
10%