a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 23

• Manufacturer Part Number: a2f500m3b-1csh484
• Description: Actel
• Manufacturer: Actel Corporation

Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
Applicable to FPGA I/O Banks
Power-Down and Sleep Mode Implementation
VJTAG and VPP should be connected to ground during Power-Down and Sleep modes. Note that when
VJTAG is not powered, the 1.5 V voltage regulator cannot be enabled through TRSTB.
VPP and VJTAG can be controlled through an external switch. Actel recommends ADG839, ADG849, or
ADG841 as possible switches.
the switch can be connected to PTBASE of the SmartFusion device. VJTAG can be controlled in same
manner.
Figure 2-2 • Implementation to Control VPP
Power per I/O Pin
SmartFusion
PTBASE
PTEM
VCCFPGAIOBx (V)
Figure 2-2
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
3.3 V
shows the implementation for controlling VPP. The IN signal of
R e v i s i o n 3
External
Pass Transister
2N2222
1.5 V
VPP Supply
Static Power
PDC7 (mW)
Actel SmartFusion Intelligent Mixed Signal FPGAs
2.26
5.72
–
–
–
–
–
–
IN
S
ADG841
Dynamic Power PAC9
(µW/MHz)
16.22
17.64
17.64
4.65
1.65
0.98
0.95
1.63
VPP Pin of
SmartFusion
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