tmp89fm42l TOSHIBA Semiconductor CORPORATION, tmp89fm42l Datasheet - Page 90

• Manufacturer Part Number: tmp89fm42l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.2
Control
RA000
5.2
Watchdog timer control register
Watchdog timer control code register
(0x0FD4)
(0x0FD5)
WDCDR
WDCTR
code register (WDCDR), the watchdog timer counter monitor (WDCNT) and the watchdog timer status (WDST).
Control
The watchdog timer is controlled by the watchdog timer control register (WDCTR), the watchdog timer control
The watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished.
Note 1: fcgck, Gear clock [Hz]; fs, Low frequency clock [Hz]
Note 2: WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> cannot be changed when WDCTR<WDTEN> is "1". If
Note 3: Bit 7 and bit 6 of WDCTR are read as "1" and "0" respectively.
WDTOUT
WDTCR2
WDTEN
Read/Write
Read/Write
Bit Symbol
WDTW
Bit Symbol
After reset
WDCTR<WDTEN> is "1", clear WDCTR<WDTEN> to "0" and write the disable code (0xB1) into WDCDR to disable the
watchdog timer operation. Note that WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> can be changed at
the same time as setting WDCTR<WDTEN> to "1".
After reset
WDTT
Enables/disables the watchdog tim-
er operation.
Sets the clear time of the 8-bit up
counter.
Sets the overflow time of the 8-bit up
counter.
Selects an overflow detection signal
of the 8-bit up counter.
Writes watchdog timer control co-
des.
R
7
1
7
0
-
R
6
0
6
0
-
WDTEN
R/W
5
1
5
0
00 :
01 :
10 :
11 :
00 :
01:
11:
Others :
Page 76
10:
0 :
1 :
0 :
1 :
0x4E :
0xB1 :
Disable
Enable
The 8-bit up counter is cleared by writing the clear code at any point within
the overflow time of the 8-bit up counter.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first quarter of the overflow time of the 8-bit up counter.
The 8-bit up counter is cleared by writing the clear code after the first quarter
of the overflow time has elapsed.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first half of the overflow time of the 8-bit up counter.
The 8-bit up counter is cleared by writing the clear code after the first half
of the overflow time has elapsed.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first three quarters of the overflow time of the 8-bit up
counter. The 8-bit up counter is cleared by writing the clear code after the
first three quarters of the overflow time have elapsed.
Watchdog timer interrupt request signal
Watchdog timer reset request signal
Clears the watchdog timer. (Clear code)
Disables the watchdog timer operation and clears the 8-bit up counter
when WDCTR<WDTEN> is "0". (Disable code)
Invalid
DV9CK=0
2
2
2
2
4
0
18
22
24
4
0
20/
/fcgck
/fcgck
/fcgck
fcgck
WDTCR2
WDTW
R/W
W
NORMAL mode
3
0
3
0
DV9CK=1
2
2
2
2
11
13
15
17
/fs
/fs
/fs
/fs
2
1
2
0
WDTT
R/W
1
1
1
0
TMP89FM42L
SLOW mode
2
2
2
2
11
13
15
17
/fs
/fs
/fs
/fs
WDTOUT
R/W
0
0
0
0