tmp89fm42l TOSHIBA Semiconductor CORPORATION, tmp89fm42l Datasheet - Page 80

• Manufacturer Part Number: tmp89fm42l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

4.2
Control
RA000
Low power consumption register 3
External interrupt control register 1
POFFCR3
EINTCR1
(0x0FD8)
(0x0F77)
Note 1: Clearing INTxEN(x=0 to 5) to "0" stops the clock supply to the external interrupts. This invalidates the data written in the
Note 2: Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corresponding
Note 3: Bits 7 and 6 of POFFSET3 are read as "0".
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
control register for each external interrupt. When using the external interrupts, set INTxEN to "1" and then write data into
the control register for each external interrupt.
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2
or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And
when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after
the operation mode is changed and clear the interrupt latch.
INT5EN
INT4EN
INT3EN
INT2EN
INT1EN
INT0EN
INI1LVL
INT1ES
INT1NC
Read/Write
Read/Write
Bit Symbol
Bit Symbol
After reset
After reset
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
INT5 control
INT4 control
INT3 control
INT2 control
INT1 control
INT0 control
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 1
Selects the interrupt request gener-
ating condition for external interrupt
1
Sets the noise canceller sampling in-
terval for external interrupt 1
R/W
R
7
0
7
0
-
-
R/W
R
6
0
6
0
-
-
INT5EN
R/W
R
5
0
5
0
-
00 :
01 :
10 :
11 :
00 :
01 :
10 :
11 :
Page 66
0 :
1 :
0
1
0
1
0
1
0
1
0
1
0
1
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller pass
signal
Reserved
fcgck [Hz]
fcgck / 2
fcgck / 2
fcgck / 2
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
INT1LVL
INT4EN
NORMAL1/2, IDLE1/2
R/W
R
4
0
4
0
2
3
4
[Hz]
[Hz]
[Hz]
INT3EN
R/W
3
0
3
INT1ES
R/W
0
INT2EN
00 :
01 :
10 :
11 :
R/W
2
0
2
fs/4 [Hz]
fs/4 [Hz]
fs/4 [Hz]
fs/4 [Hz]
SLOW1/2, SLEEP1
INT1EN
R/W
1
0
1
TMP89FM42L
INT1NC
R/W
0
INT0EN
R/W
0
0
0