tmp89fm42l TOSHIBA Semiconductor CORPORATION, tmp89fm42l Datasheet - Page 249

• Manufacturer Part Number: tmp89fm42l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
16.10
Table 16-8 Received Data Noise Rejection Time
RXDNC
00
01
10
11
in Table 16-8.
RT clock
RXD0 pin
Internal received
data
Shift register
Note 1: The transfer base clock frequency is the clock frequency selected at UARTCR1<BRG>.
When noise rejection is enabled at UART0CR2<RXDNC>, the time of pulses to be regarded as signals is as shown
Received Data Noise Rejection
2 × (UART0DR+1)/(Transfer base clock frequency)
4 × (UART0DR+1)/(Transfer base clock frequency)
(UART0DR+1)/(Transfer base clock frequency)
Noise
Noise is removed
Noise rejection time [s]
No noise rejection
Figure 16-9 Received Data Noise Rejection
A falling edge
is detected
15 14 13 12 11 10 9
Start bit
Start bit
When the noise rejection
circuit is used
Page 235
because the start bit is 0
Receiving continues
8
7
6
5
2 × (UART0DR+1)/(Transfer base clock frequency)
4 × (UART0DR+1)/(Transfer base clock frequency)
8 × (UART0DR+1)/(Transfer base clock frequency)
4
Time of pulses to be regarded as signals
3
2
1 0 15 14 13 12 11 10 9
Bit 0
Bit 0
The received data is taken into
-
the shift register
8
TMP89FM42L
7
6
5
Bit 0
4 3