lh28f016sc-l Sharp Microelectronics of the Americas, lh28f016sc-l Datasheet - Page 8

• Manufacturer Part Number: lh28f016sc-l
• Description: M-bit Smartvoltage Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

software to suspend a block erase to read/write
data from/to blocks other than that which is
suspended. Byte write suspend allows system
software to suspend a byte write to read data from
any other flash memory array location.
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to V
accommodates
encourages optimization of the processor-memory
interface.
When V
altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V
functions are disabled when V
lockout voltage V
device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and byte write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Information can be read from any block, identifier
codes, or status register independent of the V
voltage. RP# can be at either V
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
Read
PP
≤ V
PPLK
LKO
either
, memory contents cannot be
or when RP# is at V
design
PPH1/2/3
CC
IH
PP
is below the write
or V
power supply
practice
. The device
PP
HH
. All write
.
IL
. The
and
PP
- 8 -
in and out of the component : CE#, OE#, WE#,
and RP#. CE# and OE# must be driven active to
obtain data at the outputs. CE# is the device
selection control, and when active enables the
selected memory device. OE# is the data output
(DQ
selected memory data onto the I/O bus. WE# must
be at V
illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
0
-DQ
IH
IL
7
and RP# must be at V
) control and when active drives the
initiates the deep power-down mode.
0
LH28F016SC-L/SCH-L
-DQ
IH
) places the device in
7
outputs are placed
IH
PHQV
or V
IH
), the device
HH
is required
0
-DQ
. Fig. 13
7
are