lh28f016sc-l Sharp Microelectronics of the Americas, lh28f016sc-l Datasheet - Page 10

• Manufacturer Part Number: lh28f016sc-l
• Description: M-bit Smartvoltage Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
block erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require
the command and address within the device
(Master Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.
The CUI does not occupy an addressable memory
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
2. X can be V
3. RY/BY# is V
4. RP# at GND±0.2 V ensures the lowest deep power-
Read
Output Disable
Standby
Deep Power-Down
Read Identifier Codes
Write
PP
When V
not altered.
V
CHARACTERISTICS" for V
block erase, byte write, or lock-bit configuration
algorithms. It is V
in block erase suspend mode (with byte write inactive),
byte write suspend mode, or deep power-down mode.
down current.
PPLK
= V
MODE
or V
PPH1/2/3
PP
≤ V
IL
PPH1/2/3
or V
OL
PPLK
, the CUI additionally controls
when the WSM is executing internal
OH
IH
, memory contents can be read, but
for control pins and addresses, and
for V
during when the WSM is not busy,
1, 2, 3, 8 V
3, 6, 7, 8 V
PP
NOTE
PPLK
. See Section 6.2.3 "DC
3
3
4
8
and V
V
V
V
IH
IH
IH
IH
IH
PPH1/2/3
RP#
V
or V
or V
or V
or V
or V
IL
HH
HH
HH
HH
HH
Table 2 Bus Operations
voltages.
CE#
V
V
V
V
V
X
IH
IL
IL
IL
IL
- 10 -
OE#
V
V
V
V
X
X
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the V
from the status register, identifier codes, or blocks
are enabled. Placing V
successful block erase, byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, byte write, or
7. Refer to Table 3 for valid D
8. Don't use the timing both OE# and WE# are V
IH
IH
IL
IL
lock-bit configuration are reliably executed when V
V
lock-bit configuration with V
V
attempted.
PPH1/2/3
HH
WE#
V
V
V
V
produce spurious results and should not be
X
X
IH
IH
IH
IL
and V
PP
See Fig. 2
ADDRESS
voltage ≤ V
CC
X
X
X
X
X
= V
CC2/3/4
LH28F016SC-L/SCH-L
PPH1/2/3
V
IN
X
X
X
X
X
X
PP
CC
. Block erase, byte write, or
PPLK
during a write operation.
< 3.0 V or V
, read operations
(NOTE 5)
on V
High Z
High Z
High Z
DQ
D
D
OUT
IN
0-7
PP
IH
RY/BY#
IL
enables
< RP# <
.
V
V
X
X
X
X
OH
OH
PP
=